[−][src]Struct cc13x2_cc26x2_hal::ssi0::mis::R
Value read from the register
Methods
impl R
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pub fn bits(&self) -> u32
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Value of the register as raw bits
pub fn txmis(&self) -> TXMISR
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Bit 3 - 3:3] Masked interrupt state of transmit FIFO interrupt: This field returns the masked interrupt state of transmit FIFO interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM.
pub fn rxmis(&self) -> RXMISR
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Bit 2 - 2:2] Masked interrupt state of receive FIFO interrupt: This field returns the masked interrupt state of receive FIFO interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM.
pub fn rtmis(&self) -> RTMISR
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Bit 1 - 1:1] Masked interrupt state of receive timeout interrupt: This field returns the masked interrupt state of receive timeout interrupt which is the AND product of raw interrupt state RIS.RTRIS and the mask setting IMSC.RTIM.
pub fn rormis(&self) -> RORMISR
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Bit 0 - 0:0] Masked interrupt state of receive overrun interrupt: This field returns the masked interrupt state of receive overrun interrupt which is the AND product of raw interrupt state RIS.RORRIS and the mask setting IMSC.RORIM.
Auto Trait Implementations
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impl<T> From for T
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