[−][src]Struct cc13x2_cc26x2_hal::event::RegisterBlock

#[repr(C)]

pub struct RegisterBlock {
    pub cpuirqsel0: CPUIRQSEL0,
    pub cpuirqsel1: CPUIRQSEL1,
    pub cpuirqsel2: CPUIRQSEL2,
    pub cpuirqsel3: CPUIRQSEL3,
    pub cpuirqsel4: CPUIRQSEL4,
    pub cpuirqsel5: CPUIRQSEL5,
    pub cpuirqsel6: CPUIRQSEL6,
    pub cpuirqsel7: CPUIRQSEL7,
    pub cpuirqsel8: CPUIRQSEL8,
    pub cpuirqsel9: CPUIRQSEL9,
    pub cpuirqsel10: CPUIRQSEL10,
    pub cpuirqsel11: CPUIRQSEL11,
    pub cpuirqsel12: CPUIRQSEL12,
    pub cpuirqsel13: CPUIRQSEL13,
    pub cpuirqsel14: CPUIRQSEL14,
    pub cpuirqsel15: CPUIRQSEL15,
    pub cpuirqsel16: CPUIRQSEL16,
    pub cpuirqsel17: CPUIRQSEL17,
    pub cpuirqsel18: CPUIRQSEL18,
    pub cpuirqsel19: CPUIRQSEL19,
    pub cpuirqsel20: CPUIRQSEL20,
    pub cpuirqsel21: CPUIRQSEL21,
    pub cpuirqsel22: CPUIRQSEL22,
    pub cpuirqsel23: CPUIRQSEL23,
    pub cpuirqsel24: CPUIRQSEL24,
    pub cpuirqsel25: CPUIRQSEL25,
    pub cpuirqsel26: CPUIRQSEL26,
    pub cpuirqsel27: CPUIRQSEL27,
    pub cpuirqsel28: CPUIRQSEL28,
    pub cpuirqsel29: CPUIRQSEL29,
    pub cpuirqsel30: CPUIRQSEL30,
    pub cpuirqsel31: CPUIRQSEL31,
    pub cpuirqsel32: CPUIRQSEL32,
    pub cpuirqsel33: CPUIRQSEL33,
    pub cpuirqsel34: CPUIRQSEL34,
    pub cpuirqsel35: CPUIRQSEL35,
    pub cpuirqsel36: CPUIRQSEL36,
    pub cpuirqsel37: CPUIRQSEL37,
    pub rfcsel0: RFCSEL0,
    pub rfcsel1: RFCSEL1,
    pub rfcsel2: RFCSEL2,
    pub rfcsel3: RFCSEL3,
    pub rfcsel4: RFCSEL4,
    pub rfcsel5: RFCSEL5,
    pub rfcsel6: RFCSEL6,
    pub rfcsel7: RFCSEL7,
    pub rfcsel8: RFCSEL8,
    pub rfcsel9: RFCSEL9,
    pub gpt0acaptsel: GPT0ACAPTSEL,
    pub gpt0bcaptsel: GPT0BCAPTSEL,
    pub gpt1acaptsel: GPT1ACAPTSEL,
    pub gpt1bcaptsel: GPT1BCAPTSEL,
    pub gpt2acaptsel: GPT2ACAPTSEL,
    pub gpt2bcaptsel: GPT2BCAPTSEL,
    pub udmach0ssel: UDMACH0SSEL,
    pub udmach0bsel: UDMACH0BSEL,
    pub udmach1ssel: UDMACH1SSEL,
    pub udmach1bsel: UDMACH1BSEL,
    pub udmach2ssel: UDMACH2SSEL,
    pub udmach2bsel: UDMACH2BSEL,
    pub udmach3ssel: UDMACH3SSEL,
    pub udmach3bsel: UDMACH3BSEL,
    pub udmach4ssel: UDMACH4SSEL,
    pub udmach4bsel: UDMACH4BSEL,
    pub udmach5ssel: UDMACH5SSEL,
    pub udmach5bsel: UDMACH5BSEL,
    pub udmach6ssel: UDMACH6SSEL,
    pub udmach6bsel: UDMACH6BSEL,
    pub udmach7ssel: UDMACH7SSEL,
    pub udmach7bsel: UDMACH7BSEL,
    pub udmach8ssel: UDMACH8SSEL,
    pub udmach8bsel: UDMACH8BSEL,
    pub udmach9ssel: UDMACH9SSEL,
    pub udmach9bsel: UDMACH9BSEL,
    pub udmach10ssel: UDMACH10SSEL,
    pub udmach10bsel: UDMACH10BSEL,
    pub udmach11ssel: UDMACH11SSEL,
    pub udmach11bsel: UDMACH11BSEL,
    pub udmach12ssel: UDMACH12SSEL,
    pub udmach12bsel: UDMACH12BSEL,
    pub udmach13ssel: UDMACH13SSEL,
    pub udmach13bsel: UDMACH13BSEL,
    pub udmach14ssel: UDMACH14SSEL,
    pub udmach14bsel: UDMACH14BSEL,
    pub udmach15ssel: UDMACH15SSEL,
    pub udmach15bsel: UDMACH15BSEL,
    pub udmach16ssel: UDMACH16SSEL,
    pub udmach16bsel: UDMACH16BSEL,
    pub udmach17ssel: UDMACH17SSEL,
    pub udmach17bsel: UDMACH17BSEL,
    pub udmach18ssel: UDMACH18SSEL,
    pub udmach18bsel: UDMACH18BSEL,
    pub udmach19ssel: UDMACH19SSEL,
    pub udmach19bsel: UDMACH19BSEL,
    pub udmach20ssel: UDMACH20SSEL,
    pub udmach20bsel: UDMACH20BSEL,
    pub udmach21ssel: UDMACH21SSEL,
    pub udmach21bsel: UDMACH21BSEL,
    pub udmach22ssel: UDMACH22SSEL,
    pub udmach22bsel: UDMACH22BSEL,
    pub udmach23ssel: UDMACH23SSEL,
    pub udmach23bsel: UDMACH23BSEL,
    pub udmach24ssel: UDMACH24SSEL,
    pub udmach24bsel: UDMACH24BSEL,
    pub udmach25ssel: UDMACH25SSEL,
    pub udmach25bsel: UDMACH25BSEL,
    pub udmach26ssel: UDMACH26SSEL,
    pub udmach26bsel: UDMACH26BSEL,
    pub udmach27ssel: UDMACH27SSEL,
    pub udmach27bsel: UDMACH27BSEL,
    pub udmach28ssel: UDMACH28SSEL,
    pub udmach28bsel: UDMACH28BSEL,
    pub udmach29ssel: UDMACH29SSEL,
    pub udmach29bsel: UDMACH29BSEL,
    pub udmach30ssel: UDMACH30SSEL,
    pub udmach30bsel: UDMACH30BSEL,
    pub udmach31ssel: UDMACH31SSEL,
    pub udmach31bsel: UDMACH31BSEL,
    pub gpt3acaptsel: GPT3ACAPTSEL,
    pub gpt3bcaptsel: GPT3BCAPTSEL,
    pub auxsel0: AUXSEL0,
    pub cm3nmisel0: CM3NMISEL0,
    pub i2sstmpsel0: I2SSTMPSEL0,
    pub frzsel0: FRZSEL0,
    pub swev: SWEV,
    // some fields omitted
}

Register block

Fields

cpuirqsel0: CPUIRQSEL0

0x00 - Output Selection for CPU Interrupt 0

cpuirqsel1: CPUIRQSEL1

0x04 - Output Selection for CPU Interrupt 1

cpuirqsel2: CPUIRQSEL2

0x08 - Output Selection for CPU Interrupt 2

cpuirqsel3: CPUIRQSEL3

0x0c - Output Selection for CPU Interrupt 3

cpuirqsel4: CPUIRQSEL4

0x10 - Output Selection for CPU Interrupt 4

cpuirqsel5: CPUIRQSEL5

0x14 - Output Selection for CPU Interrupt 5

cpuirqsel6: CPUIRQSEL6

0x18 - Output Selection for CPU Interrupt 6

cpuirqsel7: CPUIRQSEL7

0x1c - Output Selection for CPU Interrupt 7

cpuirqsel8: CPUIRQSEL8

0x20 - Output Selection for CPU Interrupt 8

cpuirqsel9: CPUIRQSEL9

0x24 - Output Selection for CPU Interrupt 9

cpuirqsel10: CPUIRQSEL10

0x28 - Output Selection for CPU Interrupt 10

cpuirqsel11: CPUIRQSEL11

0x2c - Output Selection for CPU Interrupt 11

cpuirqsel12: CPUIRQSEL12

0x30 - Output Selection for CPU Interrupt 12

cpuirqsel13: CPUIRQSEL13

0x34 - Output Selection for CPU Interrupt 13

cpuirqsel14: CPUIRQSEL14

0x38 - Output Selection for CPU Interrupt 14

cpuirqsel15: CPUIRQSEL15

0x3c - Output Selection for CPU Interrupt 15

cpuirqsel16: CPUIRQSEL16

0x40 - Output Selection for CPU Interrupt 16

cpuirqsel17: CPUIRQSEL17

0x44 - Output Selection for CPU Interrupt 17

cpuirqsel18: CPUIRQSEL18

0x48 - Output Selection for CPU Interrupt 18

cpuirqsel19: CPUIRQSEL19

0x4c - Output Selection for CPU Interrupt 19

cpuirqsel20: CPUIRQSEL20

0x50 - Output Selection for CPU Interrupt 20

cpuirqsel21: CPUIRQSEL21

0x54 - Output Selection for CPU Interrupt 21

cpuirqsel22: CPUIRQSEL22

0x58 - Output Selection for CPU Interrupt 22

cpuirqsel23: CPUIRQSEL23

0x5c - Output Selection for CPU Interrupt 23

cpuirqsel24: CPUIRQSEL24

0x60 - Output Selection for CPU Interrupt 24

cpuirqsel25: CPUIRQSEL25

0x64 - Output Selection for CPU Interrupt 25

cpuirqsel26: CPUIRQSEL26

0x68 - Output Selection for CPU Interrupt 26

cpuirqsel27: CPUIRQSEL27

0x6c - Output Selection for CPU Interrupt 27

cpuirqsel28: CPUIRQSEL28

0x70 - Output Selection for CPU Interrupt 28

cpuirqsel29: CPUIRQSEL29

0x74 - Output Selection for CPU Interrupt 29

cpuirqsel30: CPUIRQSEL30

0x78 - Output Selection for CPU Interrupt 30

cpuirqsel31: CPUIRQSEL31

0x7c - Output Selection for CPU Interrupt 31

cpuirqsel32: CPUIRQSEL32

0x80 - Output Selection for CPU Interrupt 32

cpuirqsel33: CPUIRQSEL33

0x84 - Output Selection for CPU Interrupt 33

cpuirqsel34: CPUIRQSEL34

0x88 - Output Selection for CPU Interrupt 34

cpuirqsel35: CPUIRQSEL35

0x8c - Output Selection for CPU Interrupt 35

cpuirqsel36: CPUIRQSEL36

0x90 - Output Selection for CPU Interrupt 36

cpuirqsel37: CPUIRQSEL37

0x94 - Output Selection for CPU Interrupt 37

rfcsel0: RFCSEL0

0x100 - Output Selection for RFC Event 0

rfcsel1: RFCSEL1

0x104 - Output Selection for RFC Event 1

rfcsel2: RFCSEL2

0x108 - Output Selection for RFC Event 2

rfcsel3: RFCSEL3

0x10c - Output Selection for RFC Event 3

rfcsel4: RFCSEL4

0x110 - Output Selection for RFC Event 4

rfcsel5: RFCSEL5

0x114 - Output Selection for RFC Event 5

rfcsel6: RFCSEL6

0x118 - Output Selection for RFC Event 6

rfcsel7: RFCSEL7

0x11c - Output Selection for RFC Event 7

rfcsel8: RFCSEL8

0x120 - Output Selection for RFC Event 8

rfcsel9: RFCSEL9

0x124 - Output Selection for RFC Event 9

gpt0acaptsel: GPT0ACAPTSEL

0x200 - Output Selection for GPT0 0

gpt0bcaptsel: GPT0BCAPTSEL

0x204 - Output Selection for GPT0 1

gpt1acaptsel: GPT1ACAPTSEL

0x300 - Output Selection for GPT1 0

gpt1bcaptsel: GPT1BCAPTSEL

0x304 - Output Selection for GPT1 1

gpt2acaptsel: GPT2ACAPTSEL

0x400 - Output Selection for GPT2 0

gpt2bcaptsel: GPT2BCAPTSEL

0x404 - Output Selection for GPT2 1

udmach0ssel: UDMACH0SSEL

0x500 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach0bsel: UDMACH0BSEL

0x504 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach1ssel: UDMACH1SSEL

0x508 - Output Selection for DMA Channel 1 SREQ

udmach1bsel: UDMACH1BSEL

0x50c - Output Selection for DMA Channel 1 REQ

udmach2ssel: UDMACH2SSEL

0x510 - Output Selection for DMA Channel 2 SREQ

udmach2bsel: UDMACH2BSEL

0x514 - Output Selection for DMA Channel 2 REQ

udmach3ssel: UDMACH3SSEL

0x518 - Output Selection for DMA Channel 3 SREQ

udmach3bsel: UDMACH3BSEL

0x51c - Output Selection for DMA Channel 3 REQ

udmach4ssel: UDMACH4SSEL

0x520 - Output Selection for DMA Channel 4 SREQ

udmach4bsel: UDMACH4BSEL

0x524 - Output Selection for DMA Channel 4 REQ

udmach5ssel: UDMACH5SSEL

0x528 - Output Selection for DMA Channel 5 SREQ

udmach5bsel: UDMACH5BSEL

0x52c - Output Selection for DMA Channel 5 REQ

udmach6ssel: UDMACH6SSEL

0x530 - Output Selection for DMA Channel 6 SREQ

udmach6bsel: UDMACH6BSEL

0x534 - Output Selection for DMA Channel 6 REQ

udmach7ssel: UDMACH7SSEL

0x538 - Output Selection for DMA Channel 7 SREQ

udmach7bsel: UDMACH7BSEL

0x53c - Output Selection for DMA Channel 7 REQ

udmach8ssel: UDMACH8SSEL

0x540 - Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel

udmach8bsel: UDMACH8BSEL

0x544 - Output Selection for DMA Channel 8 REQ

udmach9ssel: UDMACH9SSEL

0x548 - Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS

udmach9bsel: UDMACH9BSEL

0x54c - Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS

udmach10ssel: UDMACH10SSEL

0x550 - Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS

udmach10bsel: UDMACH10BSEL

0x554 - Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS

udmach11ssel: UDMACH11SSEL

0x558 - Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS

udmach11bsel: UDMACH11BSEL

0x55c - Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS

udmach12ssel: UDMACH12SSEL

0x560 - Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS

udmach12bsel: UDMACH12BSEL

0x564 - Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS

udmach13ssel: UDMACH13SSEL

0x568 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach13bsel: UDMACH13BSEL

0x56c - Output Selection for DMA Channel 13 REQ

udmach14ssel: UDMACH14SSEL

0x570 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach14bsel: UDMACH14BSEL

0x574 - Output Selection for DMA Channel 14 REQ

udmach15ssel: UDMACH15SSEL

0x578 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach15bsel: UDMACH15BSEL

0x57c - Output Selection for DMA Channel 15 REQ

udmach16ssel: UDMACH16SSEL

0x580 - Output Selection for DMA Channel 16 SREQ

udmach16bsel: UDMACH16BSEL

0x584 - Output Selection for DMA Channel 16 REQ

udmach17ssel: UDMACH17SSEL

0x588 - Output Selection for DMA Channel 17 SREQ

udmach17bsel: UDMACH17BSEL

0x58c - Output Selection for DMA Channel 17 REQ

udmach18ssel: UDMACH18SSEL

0x590 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach18bsel: UDMACH18BSEL

0x594 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach19ssel: UDMACH19SSEL

0x598 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach19bsel: UDMACH19BSEL

0x59c - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach20ssel: UDMACH20SSEL

0x5a0 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach20bsel: UDMACH20BSEL

0x5a4 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach21ssel: UDMACH21SSEL

0x5a8 - Output Selection for DMA Channel 21 SREQ

udmach21bsel: UDMACH21BSEL

0x5ac - Output Selection for DMA Channel 21 REQ

udmach22ssel: UDMACH22SSEL

0x5b0 - Output Selection for DMA Channel 22 SREQ

udmach22bsel: UDMACH22BSEL

0x5b4 - Output Selection for DMA Channel 22 REQ

udmach23ssel: UDMACH23SSEL

0x5b8 - Output Selection for DMA Channel 23 SREQ

udmach23bsel: UDMACH23BSEL

0x5bc - Output Selection for DMA Channel 23 REQ

udmach24ssel: UDMACH24SSEL

0x5c0 - Output Selection for DMA Channel 24 SREQ

udmach24bsel: UDMACH24BSEL

0x5c4 - Output Selection for DMA Channel 24 REQ

udmach25ssel: UDMACH25SSEL

0x5c8 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach25bsel: UDMACH25BSEL

0x5cc - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach26ssel: UDMACH26SSEL

0x5d0 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach26bsel: UDMACH26BSEL

0x5d4 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach27ssel: UDMACH27SSEL

0x5d8 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach27bsel: UDMACH27BSEL

0x5dc - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach28ssel: UDMACH28SSEL

0x5e0 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach28bsel: UDMACH28BSEL

0x5e4 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach29ssel: UDMACH29SSEL

0x5e8 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach29bsel: UDMACH29BSEL

0x5ec - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach30ssel: UDMACH30SSEL

0x5f0 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach30bsel: UDMACH30BSEL

0x5f4 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach31ssel: UDMACH31SSEL

0x5f8 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

udmach31bsel: UDMACH31BSEL

0x5fc - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

gpt3acaptsel: GPT3ACAPTSEL

0x600 - Output Selection for GPT3 0

gpt3bcaptsel: GPT3BCAPTSEL

0x604 - Output Selection for GPT3 1

auxsel0: AUXSEL0

0x700 - Output Selection for AUX Subscriber 0

cm3nmisel0: CM3NMISEL0

0x800 - Output Selection for NMI Subscriber 0

i2sstmpsel0: I2SSTMPSEL0

0x900 - Output Selection for I2S Subscriber 0

frzsel0: FRZSEL0

0xa00 - Output Selection for FRZ Subscriber The halted debug signal is passed to peripherals such as the General Purpose Timer, Sensor Controller with Digital and Analog Peripherals (AUX), Radio, and RTC. When the system CPU halts, the connected peripherals that have freeze enabled also halt. The programmable output can be set to static values of 0 or 1, and can also be set to pass the halted signal.

swev: SWEV

0xf00 - Set or Clear Software Events

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