Struct cc13x2_cc26x2_hal::uart1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub dr: DR,
    pub rsr: RSR,
    pub reserved0: RESERVED0,
    pub fr: FR,
    pub reserved2: RESERVED2,
    pub ibrd: IBRD,
    pub fbrd: FBRD,
    pub lcrh: LCRH,
    pub ctl: CTL,
    pub ifls: IFLS,
    pub imsc: IMSC,
    pub ris: RIS,
    pub mis: MIS,
    pub icr: ICR,
    pub dmactl: DMACTL,
    pub reserved1: RESERVED1,
    pub reserved3: RESERVED3,
    pub reserved4: RESERVED4,
    // some fields omitted
}

Register block

Fields

dr: DR

0x00 - Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR register.

rsr: RSR

0x04 - Status This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status information for overrun is set immediately when an overrun condition occurs.

reserved0: RESERVED0

0x08 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

fr: FR

0x18 - Flag Reads from this register return the UART flags.

reserved2: RESERVED2

0x1c - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

ibrd: IBRD

0x24 - Integer Baud-Rate Divisor If this register is modified while transmission or reception is on-going, the baud rate will not be updated until transmission or reception of the current character is complete.

fbrd: FBRD

0x28 - Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete.

lcrh: LCRH

0x2c - Line Control

ctl: CTL

0x30 - Control

ifls: IFLS

0x34 - Interrupt FIFO Level Select

imsc: IMSC

0x38 - Interrupt Mask Set/Clear

ris: RIS

0x3c - Raw Interrupt Status

mis: MIS

0x40 - Masked Interrupt Status

icr: ICR

0x44 - Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

dmactl: DMACTL

0x48 - DMA Control

reserved1: RESERVED1

0x4c - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

reserved3: RESERVED3

0x90 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

reserved4: RESERVED4

0xfd0 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.