Struct cc13x2_cc26x2_hal::uart0::fr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved1(&self) -> RESERVED1R

Bits 8:31 - 31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn txfe(&self) -> TXFER

Bit 7 - 7:7] UART Transmit FIFO Empty: The meaning of this bit depends on the state of LCRH.FEN . - If the FIFO is disabled, this bit is set when the transmit holding register is empty. - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.

pub fn rxff(&self) -> RXFFR

Bit 6 - 6:6] UART Receive FIFO Full: The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is full. - If the FIFO is enabled, this bit is set when the receive FIFO is full.

pub fn txff(&self) -> TXFFR

Bit 5 - 5:5] UART Transmit FIFO Full: Transmit FIFO full. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the transmit holding register is full. - If the FIFO is enabled, this bit is set when the transmit FIFO is full.

pub fn rxfe(&self) -> RXFER

Bit 4 - 4:4] UART Receive FIFO Empty: Receive FIFO empty. The meaning of this bit depends on the state of LCRH.FEN. - If the FIFO is disabled, this bit is set when the receive holding register is empty. - If the FIFO is enabled, this bit is set when the receive FIFO is empty.

pub fn busy(&self) -> BUSYR

Bit 3 - 3:3] UART Busy: If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.

pub fn reserved0(&self) -> RESERVED0R

Bits 1:2 - 2:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn cts(&self) -> CTSR

Bit 0 - 0:0] Clear To Send: This bit is the complement of the active-low UART CTS input pin. That is, the bit is 1 when CTS input pin is LOW.