Struct cc13x2_cc26x2_hal::gpt3::tamr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved16(&mut self) -> _RESERVED16W

Bits 16:31 - 31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn tcact(&mut self) -> _TCACTW

Bits 13:15 - 15:13] Timer Compare Action Select

pub fn tacintd(&mut self) -> _TACINTDW

Bit 12 - 12:12] One-Shot/Periodic Interrupt Disable

pub fn taplo(&mut self) -> _TAPLOW

Bit 11 - 11:11] GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode.

pub fn tamrsu(&mut self) -> _TAMRSUW

Bit 10 - 10:10] Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit.

pub fn tapwmie(&mut self) -> _TAPWMIEW

Bit 9 - 9:9] GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode.

pub fn taild(&mut self) -> _TAILDW

Bit 8 - 8:8] GPT Timer A PWM Interval Load Write

pub fn tasnaps(&mut self) -> _TASNAPSW

Bit 7 - 7:7] GPT Timer A Snap-Shot Mode

pub fn tawot(&mut self) -> _TAWOTW

Bit 6 - 6:6] GPT Timer A Wait-On-Trigger

pub fn tamie(&mut self) -> _TAMIEW

Bit 5 - 5:5] GPT Timer A Match Interrupt Enable

pub fn tacdir(&mut self) -> _TACDIRW

Bit 4 - 4:4] GPT Timer A Count Direction

pub fn taams(&mut self) -> _TAAMSW

Bit 3 - 3:3] GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2.

pub fn tacm(&mut self) -> _TACMW

Bit 2 - 2:2] GPT Timer A Capture Mode

pub fn tamr(&mut self) -> _TAMRW

Bits 0:1 - 1:0] GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register