Struct cc13x2_cc26x2_hal::gpt2::ris::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved14(&self) -> RESERVED14R

Bits 14:31 - 31:14] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn dmabris(&self) -> DMABRISR

Bit 13 - 13:13] GPT Timer B DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed

pub fn reserved12(&self) -> RESERVED12R

Bit 12 - 12:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn tbmris(&self) -> TBMRISR

Bit 11 - 11:11] GPT Timer B Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR have been reached when configured in one-shot or periodic mode.

pub fn cberis(&self) -> CBERISR

Bit 10 - 10:10] GPT Timer B Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode

pub fn cbmris(&self) -> CBMRISR

Bit 9 - 9:9] GPT Timer B Capture Mode Match Raw Interrupt 0: The capture mode match for Timer B has not occurred. 1: A capture mode match has occurred for Timer B. This interrupt asserts when the values in the TBR and TBPR match the values in the TBMATCHR and TBPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CBMCINT bit.

pub fn tbtoris(&self) -> TBTORISR

Bit 8 - 8:8] GPT Timer B Time-out Raw Interrupt 0: Timer B has not timed out 1: Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TBILR, depending on the count direction.

pub fn reserved6(&self) -> RESERVED6R

Bits 6:7 - 7:6] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn dmaaris(&self) -> DMAARISR

Bit 5 - 5:5] GPT Timer A DMA Done Raw Interrupt Status 0: Transfer has not completed 1: Transfer has completed

pub fn tamris(&self) -> TAMRISR

Bit 4 - 4:4] GPT Timer A Match Raw Interrupt 0: The match value has not been reached 1: The match value is reached. TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR have been reached when configured in one-shot or periodic mode.

pub fn reserved3(&self) -> RESERVED3R

Bit 3 - 3:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn caeris(&self) -> CAERISR

Bit 2 - 2:2] GPT Timer A Capture Mode Event Raw Interrupt 0: The event has not occured. 1: The event has occured. This interrupt asserts when the subtimer is configured in Input Edge-Time mode

pub fn camris(&self) -> CAMRISR

Bit 1 - 1:1] GPT Timer A Capture Mode Match Raw Interrupt 0: The capture mode match for Timer A has not occurred. 1: A capture mode match has occurred for Timer A. This interrupt asserts when the values in the TAR and TAPR match the values in the TAMATCHR and TAPMR when configured in Input Edge-Time mode. This bit is cleared by writing a 1 to the ICLR.CAMCINT bit.

pub fn tatoris(&self) -> TATORISR

Bit 0 - 0:0] GPT Timer A Time-out Raw Interrupt 0: Timer A has not timed out 1: Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit. The count limit is 0 or the value loaded into TAILR, depending on the count direction.