[−][src]Struct cc13x2_cc26x2_hal::gpt0::tamr::R
Value read from the register
Methods
impl R
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pub fn bits(&self) -> u32
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Value of the register as raw bits
pub fn reserved16(&self) -> RESERVED16R
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Bits 16:31 - 31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn tcact(&self) -> TCACTR
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Bits 13:15 - 15:13] Timer Compare Action Select
pub fn tacintd(&self) -> TACINTDR
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Bit 12 - 12:12] One-Shot/Periodic Interrupt Disable
pub fn taplo(&self) -> TAPLOR
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Bit 11 - 11:11] GPTM Timer A PWM Legacy Operation 0 Legacy operation with CCP pin driven Low when the TAILR register is reloaded after the timer reaches 0. 1 CCP is driven High when the TAILR register is reloaded after the timer reaches 0. This bit is only valid in PWM mode.
pub fn tamrsu(&self) -> TAMRSUR
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Bit 10 - 10:10] Timer A Match Register Update mode This bit defines when the TAMATCHR and TAPR registers are updated. If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and TAPR are updated when the timer is enabled. If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and TAPR are updated according to the configuration of this bit.
pub fn tapwmie(&self) -> TAPWMIER
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Bit 9 - 9:9] GPTM Timer A PWM Interrupt Enable This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the CTL.TAEVENT In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit respectively. 0 Capture event interrupt is disabled. 1 Capture event interrupt is enabled. This bit is only valid in PWM mode.
pub fn taild(&self) -> TAILDR
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Bit 8 - 8:8] GPT Timer A PWM Interval Load Write
pub fn tasnaps(&self) -> TASNAPSR
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Bit 7 - 7:7] GPT Timer A Snap-Shot Mode
pub fn tawot(&self) -> TAWOTR
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Bit 6 - 6:6] GPT Timer A Wait-On-Trigger
pub fn tamie(&self) -> TAMIER
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Bit 5 - 5:5] GPT Timer A Match Interrupt Enable
pub fn tacdir(&self) -> TACDIRR
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Bit 4 - 4:4] GPT Timer A Count Direction
pub fn taams(&self) -> TAAMSR
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Bit 3 - 3:3] GPT Timer A Alternate Mode Note: To enable PWM mode, you must also clear TACM and then configure TAMR field to 0x2.
pub fn tacm(&self) -> TACMR
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Bit 2 - 2:2] GPT Timer A Capture Mode
pub fn tamr(&self) -> TAMRR
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Bits 0:1 - 1:0] GPT Timer A Mode 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the CFG register
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