Struct cc13x2_cc26x2_hal::gpt0::TAMATCHR

pub struct TAMATCHR { /* fields omitted */ }

Timer A Match Register Interrupts can be generated when the timer value is equal to the value in this register in one-shot or periodic mode. In Edge-Count mode, this register along with TAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in TAILR minus this value. Note that in edge-count mode, when executing an up-count, the value of TAPR and TAILR must be greater than the value of TAPMR and this register. In PWM mode, this value along with TAILR, determines the duty cycle of the output PWM signal. When a 16/32-bit GPT is configured to one of the 32-bit modes, TAMATCHR appears as a 32-bit register. (The upper 16-bits correspond to the contents TBMATCHR). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBMATCHR. Note : This register is updated internally (takes effect) based on TAMR.TAMRSU

Methods

impl TAMATCHR

pub fn modify<F>(&self, f: F) where
    F: FnOnce(&R, &'w mut W) -> &'w mut W, 

Modifies the contents of the register

pub fn read(&self) -> R

Reads the contents of the register

pub fn write<F>(&self, f: F) where
    F: FnOnce(&mut W) -> &mut W, 

Writes to the register

pub fn reset(&self)

Writes the reset value to the register