Struct cc13x2_cc26x2_hal::cpu_scs::stcsr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved17(&self) -> RESERVED17R

Bits 17:31 - 31:17] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn countflag(&self) -> COUNTFLAGR

Bit 16 - 16:16] Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, COUNTFLAG is not changed by the debugger read.

pub fn reserved3(&self) -> RESERVED3R

Bits 3:15 - 15:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn clksource(&self) -> CLKSOURCER

Bit 2 - 2:2] Clock source: 0: External reference clock. 1: Core clock External clock is not available in this device. Writes to this field will be ignored.

pub fn tickint(&self) -> TICKINTR

Bit 1 - 1:1] 0: Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero. 1: Counting down to zero pends the SysTick handler.

pub fn enable(&self) -> ENABLER

Bit 0 - 0:0] Enable SysTick counter 0: Counter disabled 1: Counter operates in a multi-shot way. That is, counter loads with the Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads STRVR.RELOAD again, and begins counting.