Struct cc13x2_cc26x2_hal::cpu_scs::mvfr0::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn fp_rounding_modes(&self) -> FP_ROUNDING_MODESR

Bits 28:31 - 31:28] Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported.

pub fn short_vectors(&self) -> SHORT_VECTORSR

Bits 24:27 - 27:24] Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported.

pub fn square_root(&self) -> SQUARE_ROOTR

Bits 20:23 - 23:20] Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported.

pub fn divide(&self) -> DIVIDER

Bits 16:19 - 19:16] Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported.

pub fn fp_exception_trapping(&self) -> FP_EXCEPTION_TRAPPINGR

Bits 12:15 - 15:12] Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported.

pub fn double_precision(&self) -> DOUBLE_PRECISIONR

Bits 8:11 - 11:8] Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported.

pub fn single_precision(&self) -> SINGLE_PRECISIONR

Bits 4:7 - 7:4] Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported.

pub fn a_simd(&self) -> A_SIMDR

Bits 0:3 - 3:0] Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers.