Struct cc13x2_cc26x2_hal::cpu_scs::mpu_ctrl::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved3(&mut self) -> _RESERVED3W

Bits 3:31 - 31:3] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn privdefena(&mut self) -> _PRIVDEFENAW

Bit 2 - 2:2] This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit is not set, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the system partition whether this enable is set or not. If the MPU is disabled, this bit is ignored.

pub fn hfnmiena(&mut self) -> _HFNMIENAW

Bit 1 - 1:1] This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit and ENABLE are set, the MPU is enabled when in these handlers. If this bit is not set, the MPU is disabled when in these handlers, regardless of the value of ENABLE bit. If this bit is set and ENABLE is not set, behavior is unpredictable.

pub fn enable(&mut self) -> _ENABLEW

Bit 0 - 0:0] Enable MPU 0: MPU disabled 1: MPU enabled