Struct cc13x2_cc26x2_hal::cpu_itm::tcr::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved24(&mut self) -> _RESERVED24W

Bits 24:31 - 31:24] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn busy(&mut self) -> _BUSYW

Bit 23 - 23:23] Set when ITM events present and being drained.

pub fn atbid(&mut self) -> _ATBIDW

Bits 16:22 - 22:16] Trace Bus ID for CoreSight system. Optional identifier for multi-source trace stream formatting. If multi-source trace is in use, this field must be written with a non-zero value.

pub fn reserved10(&mut self) -> _RESERVED10W

Bits 10:15 - 15:10] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn tsprescale(&mut self) -> _TSPRESCALEW

Bits 8:9 - 9:8] Timestamp prescaler

pub fn reserved5(&mut self) -> _RESERVED5W

Bits 5:7 - 7:5] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn swoena(&mut self) -> _SWOENAW

Bit 4 - 4:4] Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of the timestamp counter. 0x0: Mode disabled. Timestamp counter uses system clock from the core and counts continuously. 0x1: Timestamp counter uses lineout (data related) clock from TPIU interface. The timestamp counter is held in reset while the output line is idle.

pub fn dwtena(&mut self) -> _DWTENAW

Bit 3 - 3:3] Enables the DWT stimulus (hardware event packet emission to the TPIU from the DWT)

pub fn syncena(&mut self) -> _SYNCENAW

Bit 2 - 2:2] Enables synchronization packet transmission for a synchronous TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization speed.

pub fn tsena(&mut self) -> _TSENAW

Bit 1 - 1:1] Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle.

pub fn itmena(&mut self) -> _ITMENAW

Bit 0 - 0:0] Enables ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written.