Struct cc13x2_cc26x2_hal::ccfg::ccfg_tap_dap_1::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn pbist2_tap_enable(&mut self) -> _PBIST2_TAP_ENABLEW

Bits 16:23 - 23:16] Enable PBIST2 TAP. 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST2 TAP access will remain disabled out of power-up/system-reset.

pub fn pbist1_tap_enable(&mut self) -> _PBIST1_TAP_ENABLEW

Bits 8:15 - 15:8] Enable PBIST1 TAP. 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: PBIST1 TAP access will remain disabled out of power-up/system-reset.

pub fn aon_tap_enable(&mut self) -> _AON_TAP_ENABLEW

Bits 0:7 - 7:0] Enable AON TAP 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: AON TAP access will remain disabled out of power-up/system-reset.