Struct cc13x2_cc26x2_hal::aux_timer2::precfg::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved8(&mut self) -> _RESERVED8W

Bits 8:31 - 31:8] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn clkdiv(&mut self) -> _CLKDIVW

Bits 0:7 - 7:0] Clock division. CLKDIV determines the timer clock frequency for counter, synchronization, and timer event updates. The timer clock frequency is the clock selected by AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256.