Enum cc13x2_cc26x2_hal::aux_timer2::ch3evcfg::CCACTR

pub enum CCACTR {
    PULSE_ON_CMP,
    TGL_ON_CMP,
    SET_ON_CMP,
    CLR_ON_CMP,
    SET_ON_0_TGL_ON_CMP,
    CLR_ON_0_TGL_ON_CMP,
    SET_ON_CAPT,
    PER_PULSE_WIDTH_MEAS,
    PULSE_ON_CMP_DIS,
    TGL_ON_CMP_DIS,
    SET_ON_CMP_DIS,
    CLR_ON_CMP_DIS,
    SET_ON_0_TGL_ON_CMP_DIS,
    CLR_ON_0_TGL_ON_CMP_DIS,
    SET_ON_CAPT_DIS,
    DIS,
}

Possible values of the field CCACT

Variants

PULSE_ON_CMP

Pulse on compare repeatedly.

Channel function sequence:

• Pulse enabled events when CH3CC.VALUE = CNTR.VALUE.

The event is high for two timer clock periods.

TGL_ON_CMP

Toggle on compare repeatedly.

Channel function sequence:

• Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.

SET_ON_CMP

Set on compare repeatedly.

Channel function sequence:

• Set enabled events when CH3CC.VALUE = CNTR.VALUE.

CLR_ON_CMP

Clear on compare repeatedly.

Channel function sequence:

• Clear enabled events when CH3CC.VALUE = CNTR.VALUE.

SET_ON_0_TGL_ON_CMP

Set on zero, toggle on compare repeatedly.

Channel function sequence:

• Set enabled events when CNTR.VALUE = 0.
• Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by:

When CH3CC.VALUE <= TARGET.VALUE: Duty cycle = CH3CC.VALUE / ( TARGET.VALUE + 1 ).

When CH3CC.VALUE > TARGET.VALUE: Duty cycle = 1.

Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0.

CLR_ON_0_TGL_ON_CMP

Clear on zero, toggle on compare repeatedly.

Channel function sequence:

• Clear enabled events when CNTR.VALUE = 0.
• Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.

Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by:

When CH3CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH3CC.VALUE / TARGET.VALUE ).

When CH3CC.VALUE > TARGET.VALUE: Duty cycle = 0.

Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0.

SET_ON_CAPT

Set on capture repeatedly.

Channel function sequence:

• Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE.

Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS:

• Select this function with no event enable.
• Configure CH3CCFG (optional).
• Wait for three timer clock periods as defined in PRECFG before you enable events.

These steps prevent capture events caused by expired signal values in edge-detection circuit.

PER_PULSE_WIDTH_MEAS

Period and pulse width measurement.

Continuously capture period and pulse width of the signal selected by CH3CCFG.CAPT_SRC relative to the signal edge given by CH3CCFG.EDGE.

Set enabled events when CH3CC.VALUE contains signal period and CH3PCC.VALUE contains signal pulse width.

Notes:

• Make sure that you configure CH3CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER.
• The counter restarts in the selected timer mode when CH3CC.VALUE contains the signal period.
• If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target.
• If you want to observe a timeout event configure another channel to SET_ON_CAPT.

Signal property requirements:

• Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period.
• Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period.
• Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period.

PULSE_ON_CMP_DIS

Pulse on compare, and then disable channel.

Channel function sequence:

• Pulse enabled events when CH3CC.VALUE = CNTR.VALUE.
• Disable channel.

The event is high for two timer clock periods.

TGL_ON_CMP_DIS

Toggle on compare, and then disable channel.

Channel function sequence:

• Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.
• Disable channel.

SET_ON_CMP_DIS

Set on compare, and then disable channel.

Channel function sequence:

• Set enabled events when CH3CC.VALUE = CNTR.VALUE.
• Disable channel.

CLR_ON_CMP_DIS

Clear on compare, and then disable channel.

Channel function sequence:

• Clear enabled events when CH3CC.VALUE = CNTR.VALUE.
• Disable channel.

SET_ON_0_TGL_ON_CMP_DIS

Set on zero, toggle on compare, and then disable channel.

Channel function sequence:

• Set enabled events when CNTR.VALUE = 0.
• Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.
• Disable channel.

Enabled events are cleared when CH3CC.VALUE = 0 and CNTR.VALUE = 0.

CLR_ON_0_TGL_ON_CMP_DIS

Clear on zero, toggle on compare, and then disable channel.

Channel function sequence:

• Clear enabled events when CNTR.VALUE = 0.
• Toggle enabled events when CH3CC.VALUE = CNTR.VALUE.
• Disable channel.

Enabled events are set when CH3CC.VALUE = 0 and CNTR.VALUE = 0.

SET_ON_CAPT_DIS

Set on capture, and then disable channel.

Channel function sequence:

• Set enabled events on capture event and copy CNTR.VALUE to CH3CC.VALUE.
• Disable channel.

Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS:

• Set CCACT to SET_ON_CAPT with no event enable.
• Configure CH3CCFG (optional).
• Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional.

These steps prevent capture events caused by expired signal values in edge-detection circuit.

DIS

Disable channel.

Methods

impl CCACTR

pub fn bits(&self) -> u8

Value of the field as raw bits

pub fn is_pulse_on_cmp(&self) -> bool

Checks if the value of the field is PULSE_ON_CMP

pub fn is_tgl_on_cmp(&self) -> bool

Checks if the value of the field is TGL_ON_CMP

pub fn is_set_on_cmp(&self) -> bool

Checks if the value of the field is SET_ON_CMP

pub fn is_clr_on_cmp(&self) -> bool

Checks if the value of the field is CLR_ON_CMP

pub fn is_set_on_0_tgl_on_cmp(&self) -> bool

Checks if the value of the field is SET_ON_0_TGL_ON_CMP

pub fn is_clr_on_0_tgl_on_cmp(&self) -> bool

Checks if the value of the field is CLR_ON_0_TGL_ON_CMP

pub fn is_set_on_capt(&self) -> bool

Checks if the value of the field is SET_ON_CAPT

pub fn is_per_pulse_width_meas(&self) -> bool

Checks if the value of the field is PER_PULSE_WIDTH_MEAS

pub fn is_pulse_on_cmp_dis(&self) -> bool

Checks if the value of the field is PULSE_ON_CMP_DIS

pub fn is_tgl_on_cmp_dis(&self) -> bool

Checks if the value of the field is TGL_ON_CMP_DIS

pub fn is_set_on_cmp_dis(&self) -> bool

Checks if the value of the field is SET_ON_CMP_DIS

pub fn is_clr_on_cmp_dis(&self) -> bool

Checks if the value of the field is CLR_ON_CMP_DIS

pub fn is_set_on_0_tgl_on_cmp_dis(&self) -> bool

Checks if the value of the field is SET_ON_0_TGL_ON_CMP_DIS

pub fn is_clr_on_0_tgl_on_cmp_dis(&self) -> bool

Checks if the value of the field is CLR_ON_0_TGL_ON_CMP_DIS

pub fn is_set_on_capt_dis(&self) -> bool

Checks if the value of the field is SET_ON_CAPT_DIS

pub fn is_dis(&self) -> bool

Checks if the value of the field is DIS

Trait Implementations

impl Copy for CCACTR

impl Debug for CCACTR

fn fmt(&self, f: &mut Formatter) -> Result

Formats the value using the given formatter.

impl PartialEq<CCACTR> for CCACTR

fn eq(&self, other: &CCACTR) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Clone for CCACTR

fn clone(&self) -> CCACTR

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.