Struct cc13x2_cc26x2_hal::aux_timer2::ch0evcfg::_CCACTW

pub struct _CCACTW<'a> { /* fields omitted */ }

Proxy

Methods

impl<'a> _CCACTW<'a>

pub fn variant(self, variant: CCACTW) -> &'a mut W

Writes variant to the field

pub fn pulse_on_cmp(self) -> &'a mut W

Pulse on compare repeatedly. Channel function sequence: - Pulse enabled events when CH0CC.VALUE = CNTR.VALUE. The event is high for two timer clock periods.

pub fn tgl_on_cmp(self) -> &'a mut W

Toggle on compare repeatedly. Channel function sequence: - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE.

pub fn set_on_cmp(self) -> &'a mut W

Set on compare repeatedly. Channel function sequence: - Set enabled events when CH0CC.VALUE = CNTR.VALUE.

pub fn clr_on_cmp(self) -> &'a mut W

Clear on compare repeatedly. Channel function sequence: - Clear enabled events when CH0CC.VALUE = CNTR.VALUE.

pub fn set_on_0_tgl_on_cmp(self) -> &'a mut W

Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When CH0CC.VALUE <= TARGET.VALUE: Duty cycle = CH0CC.VALUE / ( TARGET.VALUE + 1 ). When CH0CC.VALUE > TARGET.VALUE: Duty cycle = 1. Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0.

pub fn clr_on_0_tgl_on_cmp(self) -> &'a mut W

Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When CH0CC.VALUE <= TARGET.VALUE: Duty cycle = 1 - ( CH0CC.VALUE / TARGET.VALUE ). When CH0CC.VALUE > TARGET.VALUE: Duty cycle = 0. Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0.

pub fn set_on_capt(self) -> &'a mut W

Set on capture repeatedly. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Select this function with no event enable. - Configure CH0CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you enable events. These steps prevent capture events caused by expired signal values in edge-detection circuit.

pub fn per_pulse_width_meas(self) -> &'a mut W

Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by CH0CCFG.CAPT_SRC relative to the signal edge given by CH0CCFG.EDGE. Set enabled events when CH0CC.VALUE contains signal period and CH0PCC.VALUE contains signal pulse width. Notes: - Make sure that you configure CH0CCFG.CAPT_SRC and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when CH0CC.VALUE contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - If you want to observe a timeout event configure another channel to SET_ON_CAPT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.CLKDIV ) * timer clock period. - Signal Period <= 65535 * (1 + PRECFG.CLKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.CLKDIV ) * timer clock period.

pub fn pulse_on_cmp_dis(self) -> &'a mut W

Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. The event is high for two timer clock periods.

pub fn tgl_on_cmp_dis(self) -> &'a mut W

Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel.

pub fn set_on_cmp_dis(self) -> &'a mut W

Set on compare, and then disable channel. Channel function sequence: - Set enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel.

pub fn clr_on_cmp_dis(self) -> &'a mut W

Clear on compare, and then disable channel. Channel function sequence: - Clear enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel.

pub fn set_on_0_tgl_on_cmp_dis(self) -> &'a mut W

Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are cleared when CH0CC.VALUE = 0 and CNTR.VALUE = 0.

pub fn clr_on_0_tgl_on_cmp_dis(self) -> &'a mut W

Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled events when CNTR.VALUE = 0. - Toggle enabled events when CH0CC.VALUE = CNTR.VALUE. - Disable channel. Enabled events are set when CH0CC.VALUE = 0 and CNTR.VALUE = 0.

pub fn set_on_capt_dis(self) -> &'a mut W

Set on capture, and then disable channel. Channel function sequence: - Set enabled events on capture event and copy CNTR.VALUE to CH0CC.VALUE. - Disable channel. Primary use scenario is to select this function before you start the timer. Follow these steps if you need to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no event enable. - Configure CH0CCFG (optional). - Wait for three timer clock periods as defined in PRECFG before you set CCACT to SET_ON_CAPT_DIS. Event enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit.

pub fn dis(self) -> &'a mut W

Disable channel.

pub fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field