Struct cc13x2_cc26x2_hal::aux_evctl::evstat2::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn reserved16(&mut self) -> _RESERVED16W

Bits 16:31 - 31:16] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn aux_compb(&mut self) -> _AUX_COMPBW

Bit 15 - 15:15] Comparator B output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the synchronization rate for this event.

pub fn aux_compa(&mut self) -> _AUX_COMPAW

Bit 14 - 14:14] Comparator A output. Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the synchronization rate for this event.

pub fn mcu_obsmux1(&mut self) -> _MCU_OBSMUX1W

Bit 13 - 13:13] Observation input 1 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL1.

pub fn mcu_obsmux0(&mut self) -> _MCU_OBSMUX0W

Bit 12 - 12:12] Observation input 0 from IOC. This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by IOC:OBSAUXOUTPUT.SEL_MISC.

pub fn mcu_ev(&mut self) -> _MCU_EVW

Bit 11 - 11:11] Event from EVENT configured by EVENT:AUXSEL0.

pub fn aclk_ref(&mut self) -> _ACLK_REFW

Bit 10 - 10:10] TDC reference clock. It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by AUX_SYSIF:TDCREFCLKCTL.REQ.

pub fn vddr_recharge(&mut self) -> _VDDR_RECHARGEW

Bit 9 - 9:9] Event is high while the system recharges VDDR.

pub fn mcu_active(&mut self) -> _MCU_ACTIVEW

Bit 8 - 8:8] Event is high while MCU domain is active or transitions to active (GLDO or DCDC power supply state).

pub fn pwr_dwn(&mut self) -> _PWR_DWNW

Bit 7 - 7:7] Event is high while system is in powerdown (uLDO power supply).

pub fn sclk_lf(&mut self) -> _SCLK_LFW

Bit 6 - 6:6] SCLK_LF clock

pub fn aon_batmon_temp_upd(&mut self) -> _AON_BATMON_TEMP_UPDW

Bit 5 - 5:5] Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:TEMP.

pub fn aon_batmon_bat_upd(&mut self) -> _AON_BATMON_BAT_UPDW

Bit 4 - 4:4] Event is high for two SCLK_MF clock periods when there is an update of AON_BATMON:BAT.

pub fn aon_rtc_4khz(&mut self) -> _AON_RTC_4KHZW

Bit 3 - 3:3] AON_RTC:SUBSEC.VALUE bit 19. AON_RTC:CTL.RTC_4KHZ_EN enables this event.

pub fn aon_rtc_ch2_dly(&mut self) -> _AON_RTC_CH2_DLYW

Bit 2 - 2:2] AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration.

pub fn aon_rtc_ch2(&mut self) -> _AON_RTC_CH2W

Bit 1 - 1:1] AON_RTC:EVFLAGS.CH2.

pub fn manual_ev(&mut self) -> _MANUAL_EVW

Bit 0 - 0:0] Programmable event. See MANUAL for description.