Enum cc13x2_cc26x2_hal::aux_aiodio1::iomode::IO3W

pub enum IO3W {
    OPEN_SOURCE,
    OPEN_DRAIN,
    IN,
    OUT,
}

Values that can be written to the field IO3

Variants

OPEN_SOURCE

Open-Source Mode:

When IOPOE bit 3 is 0:

• If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
• If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high.

When IOPOE bit 3 is 1:

• If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.
• If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high.

OPEN_DRAIN

Open-Drain Mode:

When IOPOE bit 3 is 0:

• If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low.
• If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

When IOPOE bit 3 is 1:

• If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low.
• If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL.

IN

Input Mode:

When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer.

When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input.

OUT

Output Mode:

When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3].

When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3].