cc1101/lowlevel/registers/
config.rs

1#[derive(Copy, Clone, Debug, Eq, PartialEq)]
2pub enum Config {
3    /// GDO2 output pin configuration
4    IOCFG2 = 0x00,
5    /// GDO1 output pin configuration
6    IOCFG1 = 0x01,
7    /// GDO0 output pin configuration
8    IOCFG0 = 0x02,
9    /// RX FIFO and TX FIFO thresholds
10    FIFOTHR = 0x03,
11    /// Sync word, high byte
12    SYNC1 = 0x04,
13    /// Sync word, low byte
14    SYNC0 = 0x05,
15    /// Packet length
16    PKTLEN = 0x06,
17    /// Packet automation control
18    PKTCTRL1 = 0x07,
19    /// Packet automation control
20    PKTCTRL0 = 0x08,
21    /// Device address
22    ADDR = 0x09,
23    /// Channel number
24    CHANNR = 0x0A,
25    /// Frequency synthesizer control
26    FSCTRL1 = 0x0B,
27    /// Frequency synthesizer control
28    FSCTRL0 = 0x0C,
29    /// Frequency control word, high byte
30    FREQ2 = 0x0D,
31    /// Frequency control word, middle byte
32    FREQ1 = 0x0E,
33    /// Frequency control word, low byte
34    FREQ0 = 0x0F,
35    /// Modem configuration
36    MDMCFG4 = 0x10,
37    /// Modem configuration
38    MDMCFG3 = 0x11,
39    /// Modem configuration
40    MDMCFG2 = 0x12,
41    /// Modem configuration
42    MDMCFG1 = 0x13,
43    /// Modem configuration
44    MDMCFG0 = 0x14,
45    /// Modem deviation setting
46    DEVIATN = 0x15,
47    /// Main Radio Cntrl State Machine config
48    MCSM2 = 0x16,
49    /// Main Radio Cntrl State Machine config
50    MCSM1 = 0x17,
51    /// Main Radio Cntrl State Machine config
52    MCSM0 = 0x18,
53    /// Frequency Offset Compensation config
54    FOCCFG = 0x19,
55    /// Bit Synchronization configuration
56    BSCFG = 0x1A,
57    /// AGC control
58    AGCCTRL2 = 0x1B,
59    /// AGC control
60    AGCCTRL1 = 0x1C,
61    /// AGC control
62    AGCCTRL0 = 0x1D,
63    /// High byte Event 0 timeout
64    WOREVT1 = 0x1E,
65    /// Low byte Event 0 timeout
66    WOREVT0 = 0x1F,
67    /// Wake On Radio control
68    WORCTRL = 0x20,
69    /// Front end RX configuration
70    FREND1 = 0x21,
71    /// Front end TX configuration
72    FREND0 = 0x22,
73    /// Frequency synthesizer calibration
74    FSCAL3 = 0x23,
75    /// Frequency synthesizer calibration
76    FSCAL2 = 0x24,
77    /// Frequency synthesizer calibration
78    FSCAL1 = 0x25,
79    /// Frequency synthesizer calibration
80    FSCAL0 = 0x26,
81    /// RC oscillator configuration
82    RCCTRL1 = 0x27,
83    /// RC oscillator configuration
84    RCCTRL0 = 0x28,
85    /// Frequency synthesizer cal control
86    FSTEST = 0x29,
87    /// Production test
88    PTEST = 0x2A,
89    /// AGC test
90    AGCTEST = 0x2B,
91    /// Various test settings
92    TEST2 = 0x2C,
93    /// Various test settings
94    TEST1 = 0x2D,
95    /// Various test settings
96    TEST0 = 0x2E,
97}
98
99impl Config {
100    pub fn addr(&self) -> u8 {
101        *self as u8
102    }
103}
104
105impl From<Config> for crate::lowlevel::registers::Register {
106    fn from(val: Config) -> Self {
107        crate::lowlevel::registers::Register::Config(val)
108    }
109}
110
111register!(IOCFG2, 0b0010_1001, u8, {
112    #[doc = "Invert output, i.e. select active low (1) / high (0)"]
113    gdo2_inv @ 6,
114    #[doc = "Default is CHP_RDYn (See Table 41 on page 62)"]
115    gdo2_cfg @ 0..5,
116});
117
118register!(IOCFG1, 0b0010_1110, u8, {
119    #[doc = "Set high (1) or low (0) output drive strength on the GDO pins"]
120    gdo1_ds @ 7,
121    #[doc = "Invert output, i.e. select active low (1) / high (0)"]
122    gdo1_inv @ 6,
123    #[doc = "Default is 3-state (See Table 41 on page 62)"]
124    gdo1_cfg @ 0..5,
125});
126
127register!(IOCFG0, 0b0011_1111, u8, {
128    #[doc = "Enable analog temperature sensor. Write 0 in all other register bits when using temperature sensor."]
129    temp_sensor_enable @ 7,
130    #[doc = "Invert output, i.e. select active low (1) / high (0)"]
131    gdo0_inv @ 6,
132    #[doc = "Default is CLK_XOSC/192 (See Table 41 on page 62)."]
133    gdo0_cfg @ 0..5,
134});
135
136register!(FIFOTHR, 0b0000_0111, u8, {
137    #[doc = "Analog to Digital Converter retention"]
138    adc_retention @ 6,
139    #[doc = "RX Attenuation, see DN010 for more details"]
140    close_in_rx @ 4..5,
141    #[doc = "Set the threshold for the TX FIFO and RX FIFO"]
142    fifo_thr @ 0..3,
143});
144
145register!(SYNC1, 0b1101_0011, u8, {
146    #[doc = "8 MSB of 16-bit sync word"]
147    sync @ 0..7,
148});
149
150register!(SYNC0, 0b1001_0001, u8, {
151    #[doc = "8 LSB of 16-bit sync word"]
152    sync @ 0..7,
153});
154
155register!(PKTLEN, 0b1111_1111, u8, {
156    #[doc = "Packet length if mode is fixed, or max length if variable"]
157    packet_length @ 0..7,
158});
159
160register!(PKTCTRL1, 0b0000_0100, u8, {
161    #[doc = "Preamble quality estimator threshold."]
162    pqt @ 5..7,
163    #[doc = "Enable automatic flush of RX FIFO when CRC is not OK."]
164    crc_autoflush @ 3,
165    #[doc = "Append RSSI and LQI to RX payload"]
166    append_status @ 2,
167    #[doc = "Address check configuration of received packages"]
168    adr_chk @ 0..1,
169});
170
171register!(PKTCTRL0, 0b0100_0101, u8, {
172    #[doc = "Turn data whitening on / off"]
173    white_data @ 6,
174    #[doc = "Format of RX and TX data"]
175    pkt_format @ 4..5,
176    #[doc = "CRC calculation on / off"]
177    crc_en @ 2,
178    #[doc = "Packet length configuration"]
179    length_config @ 0..1,
180});
181
182register!(ADDR, 0b0000_0000, u8, {
183    #[doc = "Address used for packet filtration"]
184    device_addr @ 0..7,
185});
186
187register!(CHANNR, 0b0000_0000, u8, {
188    #[doc = "Channel number, which is multiplied by the channel spacing setting and added to the base frequency."]
189    chan @ 0..7,
190});
191
192register!(FSCTRL1, 0b0000_1111, u8, {
193    #[doc = "The desired IF frequency to employ in RX"]
194    freq_if @ 0..4,
195});
196
197register!(FSCTRL0, 0b0000_0000, u8, {
198    #[doc = "Frequency offset added to the base frequency before being used by the frequency synthesizer. (2-comp)"]
199    freqoff @ 0..7,
200});
201
202register!(FREQ2, 0b0001_1110, u8, {
203    #[doc = "FREQ\\[23:0\\] is the base frequency for the frequency synthesiser"]
204    freq @ 0..5,
205});
206
207register!(FREQ1, 0b1100_0100, u8, {
208    #[doc = "FREQ\\[15:8\\], see FREQ2"]
209    freq @ 0..7,
210});
211
212register!(FREQ0, 0b1110_1100, u8, {
213    #[doc = "FREQ\\[7:0\\], see FREQ2"]
214    freq @ 0..7,
215});
216
217register!(MDMCFG4, 0b1000_1100, u8, {
218    #[doc = "Exponent of channel bandwidth"]
219    chanbw_e @ 6..7,
220    #[doc = "Mantissa of channel bandwidth"]
221    chanbw_m @ 4..5,
222    #[doc = "Exponent of symbol rate"]
223    drate_e @ 0..3,
224});
225
226register!(MDMCFG3, 0b0010_0010, u8, {
227    #[doc = "Mantissa of symbol rate"]
228    drate_m @ 0..7,
229});
230
231register!(MDMCFG2, 0b0000_0010, u8, {
232    #[doc = "Disable digital DC blocking filter before demodulator"]
233    dem_dcfilt_off @ 7,
234    #[doc = "The modulation format of the radio signal"]
235    mod_format @ 4..6,
236    #[doc = "Enables Manchester encoding/decoding"]
237    manchester_en @ 3,
238    #[doc = "Combined sync-word qualifier mode"]
239    sync_mode @ 0..2,
240});
241
242register!(MDMCFG1, 0b0010_0010, u8, {
243    #[doc = "Enable Forward Error Correction"]
244    fec_en @ 7,
245    #[doc = "Sets the minimum number of preamble bytes to be transmitted"]
246    num_preamble @ 4..6,
247    #[doc = "Exponent of channel spacing"]
248    chanspc_e @ 0..1,
249});
250
251register!(MDMCFG0, 0b1111_1000, u8, {
252    #[doc = "Mantissa of channel spacing"]
253    chanspc_m @ 0..7,
254});
255
256register!(DEVIATN, 0b0100_0111, u8, {
257    #[doc = "Exponent of deviation"]
258    deviation_e @ 4..6,
259    #[doc = "Mantissa of deviation"]
260    deviation_m @ 0..2,
261});
262
263register!(MCSM2, 0b0000_0111, u8, {
264    #[doc = "Direct RX termination based on RSSI measurement"]
265    rx_time_rssi @ 4,
266    #[doc = "When RX_TIME expires, check sync_word (0), or either sync_word/PQI (1)"]
267    rx_time_qual @ 3,
268    #[doc = "Timeout for sync word search in RX for both WOR mode and normal RX operation."]
269    rx_time @ 0..2,
270
271});
272
273register!(MCSM1, 0b0011_0000, u8, {
274    #[doc = "Selects CCA_MODE; Reflected in CCA signal"]
275    cca_mode @ 4..5,
276    #[doc = "Select what should happen when a packet has been received"]
277    rxoff_mode @ 2..3,
278    #[doc = "Select what should happen when a packet has been sent"]
279    txoff_mode @ 0..1,
280});
281
282register!(MCSM0, 0b0000_0100, u8, {
283    #[doc = "Automatically calibrate when going to RX or TX, or back to IDLE"]
284    fs_autocal @ 4..5,
285    #[doc = "Programs the number of times the six-bit ripple counter must expire after XOSC has stabilized before CHP_RDYn goes low"]
286    po_timeout @ 2..3,
287    #[doc = "Enables the pin radio control option"]
288    pin_ctrl_en @ 1,
289    #[doc = "Force the XOSC to stay on in the SLEEP state"]
290    xosc_force_on @ 0,
291});
292
293register!(FOCCFG, 0b0011_0110, u8, {
294    #[doc = "If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CS signal goes high"]
295    foc_bs_cs_gate @ 5,
296    #[doc = "The frequency compensation loop gain to be used before a sync word is detected"]
297    foc_pre_k @ 3..4,
298    #[doc = "The frequency compensation loop gain to be used after a sync word is detected"]
299    foc_post_k @ 2,
300    #[doc = "The saturation point for the frequency offset compensation algorithm"]
301    foc_limit @ 0..1,
302});
303
304register!(BSCFG, 0b0110_1100, u8, {
305    #[doc = "The clock recovery feedback loop integral gain to be used before a sync word is detected"]
306    bs_pre_ki @ 6..7,
307    #[doc = "The clock recovery feedback loop proportional gain to be used before a sync word is detected"]
308    bs_pre_kp @ 4..5,
309    #[doc = "The clock recovery feedback loop integral gain to be used after a sync word is detected"]
310    bs_post_ki @ 3,
311    #[doc = "The clock recovery feedback loop proportional gain to be used after a sync word is detected"]
312    bs_post_kp @ 2,
313    #[doc = "The saturation point for the data rate offset compensation algorithm"]
314    bs_limit @ 0..1,
315});
316
317register!(AGCCTRL2, 0b0000_0011, u8, {
318    #[doc = "Reduces the maximum allowable DVGA gain"]
319    max_dvga_gain @ 6..7,
320    #[doc = "Sets the maximum allowable LNA + LNA 2 gain relative to the maximum possible gain"]
321    max_lna_gain @ 3..5,
322    #[doc = "These bits set the target value for the averaged amplitude from the digital channel filter"]
323    magn_target @ 0..2,
324});
325
326register!(AGCCTRL1, 0b0100_0000, u8, {
327    #[doc = "Selects between two different strategies for LNA and LNA 2 gain adjustment"]
328    agc_lna_priority @ 6,
329    #[doc = "Sets the relative change threshold for asserting carrier sense"]
330    carrier_sense_rel_thr @ 4..5,
331    #[doc = "Sets the absolute RSSI threshold for asserting carrier sense."]
332    carrier_sense_abs_thr @ 0..3,
333});
334
335register!(AGCCTRL0, 0b1001_0001, u8, {
336    #[doc = "Sets the level of hysteresis on the magnitude deviation"]
337    hyst_level @ 6..7,
338    #[doc = "Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples"]
339    wait_time @ 4..5,
340    #[doc = "Control when the AGC gain should be frozen"]
341    agc_freeze @ 2..3,
342    #[doc = "Filter length, in relation to MOD_FORMAT"]
343    filter_length @ 0..1,
344});
345
346register!(WOREVT1, 0b1000_0111, u8, {
347    #[doc = "High byte of EVENT0 timeout register"]
348    event @ 0..7,
349});
350
351register!(WOREVT0, 0b0110_1011, u8, {
352    #[doc = "Low byte of EVENT0 timeout register"]
353    event @ 0..7,
354});
355
356register!(WORCTRL, 0b1111_1000, u8, {
357    #[doc = "Power down signal to RC oscillator"]
358    rc_pd @ 7,
359    #[doc = "Timeout setting from register block"]
360    event @ 4..6,
361    #[doc = "Enables (1) or disables (0) the RC oscillator calibration"]
362    rc_cal @ 3,
363    #[doc = "Controls the Event 0 resolution as well as maximum timeout of the WOR module and maximum timeout under normal RX operation"]
364    wor_res @ 0..1,
365});
366
367register!(FREND1, 0b0101_0110, u8, {
368    #[doc = "Adjusts front-end LNA PTAT current output"]
369    lna_current @ 6..7,
370    #[doc = "Adjusts front-end PTAT outputs"]
371    lna2mix_current @ 4..5,
372    #[doc = "Adjusts current in RX LO buffer (LO input to mixer)"]
373    lodiv_buf_current_rx @ 2..3,
374    #[doc = "Adjusts current in mixer"]
375    mix_current @ 0..1,
376});
377
378register!(FREND0, 0b0001_0000, u8, {
379    #[doc = "Adjusts current TX LO buffer (input to PA)"]
380    lodiv_buf_current_tx @ 4..5,
381    #[doc = "Selects PA power setting"]
382    pa_power @ 0..2,
383});
384
385register!(FSCAL3, 0b1010_1001, u8, {
386    #[doc = "Frequency synthesizer calibration configuration"]
387    fscal3 @ 6..7,
388    #[doc = "Disable charge pump calibration stage when 0"]
389    chp_curr_cal_en @ 4..5,
390    #[doc = "Frequency synthesizer calibration result register"]
391    fscal3_result @ 0..3,
392});
393
394register!(FSCAL2, 0b0000_1010, u8, {
395    #[doc = "Choose high (1) / low (0) VCO"]
396    vco_core_h_en @ 5,
397    #[doc = "Frequency synthesizer calibration result register, VCO current calibration result and override value"]
398    fscal2 @ 0..4,
399});
400
401register!(FSCAL1, 0b0010_0000, u8, {
402    #[doc = "Frequency synthesizer calibration result register, capacitor array setting for VCO coarse tuning"]
403    fscal1 @ 0..5,
404});
405
406register!(FSCAL0, 0b0000_1101, u8, {
407    #[doc = "Frequency synthesizer calibration control"]
408    fscal0 @ 0..6,
409});
410
411register!(RCCTRL1, 0b0100_0001, u8, {
412    #[doc = "RC oscillator configuration"]
413    rcctrl1 @ 0..6,
414});
415
416register!(RCCTRL0, 0b0000_0000, u8, {
417    #[doc = "RC oscillator configuration."]
418    rcctrl0 @ 0..6,
419
420});
421
422register!(FSTEST, 0b0101_1001, u8, {
423    #[doc = "For test only. Do not write to this register."]
424    fstest @ 0..7,
425});
426
427register!(PTEST, 0b0111_1111, u8, {
428    #[doc = "Writing 0xBF to this register makes the on-chip temperature sensor available in the IDLE state"]
429    ptest @ 0..7,
430});
431
432register!(AGCTEST, 0b0011_1111, u8, {
433    #[doc = "For test only. Do not write to this register"]
434    agctest @ 0..7,
435});
436
437register!(TEST2, 0b1000_1000, u8, {
438    #[doc = "The value to use in this register is given by the SmartRF Studio software"]
439    test2 @ 0..7,
440});
441
442register!(TEST1, 0b0011_0001, u8, {
443    #[doc = "The value to use in this register is given by the SmartRF Studio software"]
444    test1 @ 0..7,
445});
446
447register!(TEST0, 0b0000_1011, u8, {
448    #[doc = "The value to use in this register is given by the SmartRF Studio software"]
449    test0_1 @ 2..7,
450    #[doc = "Enable VCO selection calibration stage when 1"]
451    vco_sel_cal_en @ 1,
452    #[doc = "The value to use in this register is given by the SmartRF Studio software"]
453    test0_0 @ 0,
454});
cc1101/lowlevel/registers/config.rs

cc1101/lowlevel/registers/
config.rs
