capstone_git/arch/
riscv.rs

1//! Contains riscv-specific types
2
3use core::convert::From;
4use core::{cmp, fmt, slice};
5
6// XXX todo(tmfink): create rusty versions
7pub use capstone_sys::riscv_insn_group as RiscVInsnGroup;
8pub use capstone_sys::riscv_insn as RiscVInsn;
9pub use capstone_sys::riscv_reg as RiscVReg;
10use capstone_sys::{cs_riscv, cs_riscv_op, riscv_op_mem, riscv_op_type};
11
12pub use crate::arch::arch_builder::riscv::*;
13use crate::arch::DetailsArchInsn;
14use crate::instruction::{RegId, RegIdInt};
15
16/// Contains RISCV-specific details for an instruction
17pub struct RiscVInsnDetail<'a>(pub(crate) &'a cs_riscv);
18
19impl_PartialEq_repr_fields!(RiscVInsnDetail<'a> [ 'a ];
20    operands
21);
22
23/// RISCV operand
24#[derive(Clone, Debug, Eq, PartialEq)]
25pub enum RiscVOperand {
26    /// Register
27    Reg(RegId),
28
29    /// Immediate
30    Imm(i64),
31
32    /// Memory
33    Mem(RiscVOpMem),
34
35    /// Invalid
36    Invalid,
37}
38
39impl Default for RiscVOperand {
40    fn default() -> Self {
41        RiscVOperand::Invalid
42    }
43}
44
45/// RISCV memory operand
46#[derive(Debug, Copy, Clone)]
47pub struct RiscVOpMem(pub(crate) riscv_op_mem);
48
49impl RiscVOpMem {
50    /// Base register
51    pub fn base(&self) -> RegId {
52        RegId(self.0.base as RegIdInt)
53    }
54
55    /// Disp value
56    pub fn disp(&self) -> i64 {
57        self.0.disp
58    }
59}
60
61impl_PartialEq_repr_fields!(RiscVOpMem;
62    base, disp
63);
64
65impl cmp::Eq for RiscVOpMem {}
66
67impl From<&cs_riscv_op> for RiscVOperand {
68    fn from(insn: &cs_riscv_op) -> RiscVOperand {
69        match insn.type_ {
70            riscv_op_type::RISCV_OP_REG => {
71                RiscVOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
72            }
73            riscv_op_type::RISCV_OP_IMM => RiscVOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }),
74            riscv_op_type::RISCV_OP_MEM => {
75                RiscVOperand::Mem(RiscVOpMem(unsafe { insn.__bindgen_anon_1.mem }))
76            }
77            riscv_op_type::RISCV_OP_INVALID => RiscVOperand::Invalid,
78        }
79    }
80}
81
82def_arch_details_struct!(
83    InsnDetail = RiscVInsnDetail;
84    Operand = RiscVOperand;
85    OperandIterator = RiscVOperandIterator;
86    OperandIteratorLife = RiscVOperandIterator<'a>;
87    [ pub struct RiscVOperandIterator<'a>(slice::Iter<'a, cs_riscv_op>); ]
88    cs_arch_op = cs_riscv_op;
89    cs_arch = cs_riscv;
90);
capstone_git/arch/riscv.rs

capstone_git/arch/
riscv.rs
