Module ShReg

Module ShReg 

Source

Constants§

SH_REG_DBR
SH_REG_DR0
SH_REG_DR2
SH_REG_DR4
SH_REG_DR6
SH_REG_DR8
SH_REG_DR10
SH_REG_DR12
SH_REG_DR14
SH_REG_DSP_A0
SH_REG_DSP_A0G
SH_REG_DSP_A1
SH_REG_DSP_A1G
SH_REG_DSP_DSR
SH_REG_DSP_M0
SH_REG_DSP_M1
SH_REG_DSP_RSV0
SH_REG_DSP_RSV1
SH_REG_DSP_RSV2
SH_REG_DSP_RSV3
SH_REG_DSP_RSV4
SH_REG_DSP_RSV5
SH_REG_DSP_RSV6
SH_REG_DSP_RSV7
SH_REG_DSP_RSV8
SH_REG_DSP_RSV9
SH_REG_DSP_RSVA
SH_REG_DSP_RSVB
SH_REG_DSP_RSVC
SH_REG_DSP_RSVD
SH_REG_DSP_RSVE
SH_REG_DSP_RSVF
SH_REG_DSP_X0
SH_REG_DSP_X1
SH_REG_DSP_Y0
SH_REG_DSP_Y1
SH_REG_ENDING
SH_REG_FPSCR
SH_REG_FPUL
SH_REG_FR0
SH_REG_FR1
SH_REG_FR2
SH_REG_FR3
SH_REG_FR4
SH_REG_FR5
SH_REG_FR6
SH_REG_FR7
SH_REG_FR8
SH_REG_FR9
SH_REG_FR10
SH_REG_FR11
SH_REG_FR12
SH_REG_FR13
SH_REG_FR14
SH_REG_FR15
SH_REG_FV0
SH_REG_FV4
SH_REG_FV8
SH_REG_FV12
SH_REG_GBR
SH_REG_INVALID
SH_REG_MACH
SH_REG_MACL
SH_REG_MOD
SH_REG_PC
SH_REG_PR
SH_REG_R0
SH_REG_R0_BANK
SH_REG_R1
SH_REG_R2
SH_REG_R3
SH_REG_R4
SH_REG_R5
SH_REG_R6
SH_REG_R7
SH_REG_R8
SH_REG_R9
SH_REG_R1_BANK
SH_REG_R2_BANK
SH_REG_R3_BANK
SH_REG_R4_BANK
SH_REG_R5_BANK
SH_REG_R6_BANK
SH_REG_R7_BANK
SH_REG_R10
SH_REG_R11
SH_REG_R12
SH_REG_R13
SH_REG_R14
SH_REG_R15
SH_REG_RE
SH_REG_RS
SH_REG_SGR
SH_REG_SPC
SH_REG_SR
SH_REG_SSR
SH_REG_TBR
SH_REG_VBR
SH_REG_XD0
SH_REG_XD2
SH_REG_XD4
SH_REG_XD6
SH_REG_XD8
SH_REG_XD10
SH_REG_XD12
SH_REG_XD14
SH_REG_XF0
SH_REG_XF1
SH_REG_XF2
SH_REG_XF3
SH_REG_XF4
SH_REG_XF5
SH_REG_XF6
SH_REG_XF7
SH_REG_XF8
SH_REG_XF9
SH_REG_XF10
SH_REG_XF11
SH_REG_XF12
SH_REG_XF13
SH_REG_XF14
SH_REG_XF15
SH_REG_XMATRX

Type Aliases§

Type
SH registers and special registers