calliope_common/board.rs
1// Copied from https://github.com/nrf-rs/microbit/tree/main/microbit-common/src/v1
2// ToDo: Needs Calliope adjustments
3
4use super::gpio::{
5 DisplayPins, BTN_A, BTN_B, EDGE00, EDGE01, EDGE02, EDGE08, EDGE12, EDGE16, SCL, SDA, UART_RX,
6 UART_TX,
7};
8use crate::{
9 hal::{
10 gpio::{p0, Disconnected, Level},
11 twi, uart,
12 },
13 pac,
14};
15
16/// Provides access to the microbit
17#[allow(non_snake_case)]
18pub struct Board {
19 /// GPIO pins that are not otherwise used
20 pub pins: Pins,
21
22 /// Unused GPIO pins on edge connector
23 pub edge: Edge,
24
25 /// display pins
26 pub display_pins: DisplayPins,
27
28 /// buttons
29 pub buttons: Buttons,
30
31 /// I2C shared internal and external bus pins
32 pub i2c: I2CPins,
33
34 /// UART to debugger pins
35 pub uart: UartPins,
36
37 /// Core peripheral: Cache and branch predictor maintenance operations
38 pub CBP: pac::CBP,
39
40 /// Core peripheral: CPUID
41 pub CPUID: pac::CPUID,
42
43 /// Core peripheral: Debug Control Block
44 pub DCB: pac::DCB,
45
46 /// Core peripheral: Data Watchpoint and Trace unit
47 pub DWT: pac::DWT,
48
49 /// Core peripheral: Flash Patch and Breakpoint unit
50 pub FPB: pac::FPB,
51
52 /// Core peripheral: Instrumentation Trace Macrocell
53 pub ITM: pac::ITM,
54
55 /// Core peripheral: Memory Protection Unit
56 pub MPU: pac::MPU,
57
58 /// Core peripheral: Nested Vector Interrupt Controller
59 pub NVIC: pac::NVIC,
60
61 /// Core peripheral: System Control Block
62 pub SCB: pac::SCB,
63
64 /// Core peripheral: SysTick Timer
65 pub SYST: pac::SYST,
66
67 /// Core peripheral: Trace Port Interface Unit
68 pub TPIU: pac::TPIU,
69
70 /// nRF51 peripheral: ADC
71 pub ADC: pac::ADC,
72
73 /// nRF51 peripheral: CLOCK
74 pub CLOCK: pac::CLOCK,
75
76 /// nRF51 peripheral: FICR
77 pub FICR: pac::FICR,
78
79 /// nRF51 peripheral: GPIOTE
80 pub GPIOTE: pac::GPIOTE,
81
82 /// nRF51 preipheral: PPI
83 pub PPI: pac::PPI,
84
85 /// nRF51 peripheral: RADIO
86 pub RADIO: pac::RADIO,
87
88 /// nRF51 peripheral: RNG
89 pub RNG: pac::RNG,
90
91 /// nRF51 peripheral: RTC0
92 pub RTC0: pac::RTC0,
93
94 /// nRF51 peripheral: TEMP <br>
95 /// Can be used with [`Temp::new()`](`crate::hal::temp::Temp::new()`)
96 pub TEMP: pac::TEMP,
97
98 /// nRF51 peripheral: TIMER0
99 pub TIMER0: pac::TIMER0,
100
101 /// nRF51 peripheral: TIMER1
102 pub TIMER1: pac::TIMER1,
103
104 /// nRF51 peripheral: TIMER2
105 pub TIMER2: pac::TIMER2,
106
107 /// nRF51 peripheral: TWI0
108 pub TWI0: pac::TWI0,
109
110 /// nrf51 peripheral: UART0
111 pub UART0: pac::UART0,
112}
113
114impl Board {
115 /// Take the peripherals safely
116 ///
117 /// This method will return an instance of the board the first time it is
118 /// called. It will return only `None` on subsequent calls.
119 /// This function can also return `None` if one of the the peripherals was
120 /// already taken.
121 pub fn take() -> Option<Self> {
122 Some(Self::new(
123 pac::Peripherals::take()?,
124 pac::CorePeripherals::take()?,
125 ))
126 }
127
128 /// Fallback method in the case peripherals and core peripherals were taken
129 /// elsewhere already.
130 ///
131 /// This method will take the peripherals and core peripherals and
132 /// return an instance of the board.
133 ///
134 /// An exemplary usecase is shown in the rtic display example.
135 pub fn new(p: pac::Peripherals, cp: pac::CorePeripherals) -> Self {
136 let p0parts = p0::Parts::new(p.GPIO);
137 Self {
138 pins: Pins {
139 //p0_01: p0parts.p0_01,
140 //p0_02: p0parts.p0_02,
141 //p0_03: p0parts.p0_03,
142 //p0_16: p0parts.p0_16,
143 //p0_18: p0parts.p0_18,
144 p0_19: p0parts.p0_19,
145 //p0_20: p0parts.p0_20,
146 p0_21: p0parts.p0_21,
147 p0_22: p0parts.p0_22,
148 p0_23: p0parts.p0_23,
149 p0_27: p0parts.p0_27,
150 p0_28: p0parts.p0_28,
151 p0_29: p0parts.p0_29,
152 },
153 edge: Edge {
154 e00: p0parts.p0_03,
155 e01: p0parts.p0_02,
156 e02: p0parts.p0_01,
157 e08: p0parts.p0_18,
158 e12: p0parts.p0_20,
159 e16: p0parts.p0_16,
160 },
161 display_pins: DisplayPins {
162 row1: p0parts.p0_13.into_push_pull_output(Level::Low),
163 row2: p0parts.p0_14.into_push_pull_output(Level::Low),
164 row3: p0parts.p0_15.into_push_pull_output(Level::Low),
165 col1: p0parts.p0_04.into_push_pull_output(Level::High),
166 col2: p0parts.p0_05.into_push_pull_output(Level::High),
167 col3: p0parts.p0_06.into_push_pull_output(Level::High),
168 col4: p0parts.p0_07.into_push_pull_output(Level::High),
169 col5: p0parts.p0_08.into_push_pull_output(Level::High),
170 col6: p0parts.p0_09.into_push_pull_output(Level::High),
171 col7: p0parts.p0_10.into_push_pull_output(Level::High),
172 col8: p0parts.p0_11.into_push_pull_output(Level::High),
173 col9: p0parts.p0_12.into_push_pull_output(Level::High),
174 },
175 buttons: Buttons {
176 button_a: p0parts.p0_17.into_floating_input(),
177 button_b: p0parts.p0_26.into_floating_input(),
178 },
179 i2c: I2CPins {
180 scl: p0parts.p0_00.into_floating_input(),
181 sda: p0parts.p0_30.into_floating_input(),
182 },
183 uart: UartPins {
184 tx: p0parts.p0_24.into_push_pull_output(Level::Low),
185 rx: p0parts.p0_25.into_floating_input(),
186 },
187
188 // Core peripherals
189 CBP: cp.CBP,
190 CPUID: cp.CPUID,
191 DCB: cp.DCB,
192 DWT: cp.DWT,
193 FPB: cp.FPB,
194 ITM: cp.ITM,
195 MPU: cp.MPU,
196 NVIC: cp.NVIC,
197 SCB: cp.SCB,
198 SYST: cp.SYST,
199 TPIU: cp.TPIU,
200
201 // nRF51 peripherals
202 ADC: p.ADC,
203 CLOCK: p.CLOCK,
204 FICR: p.FICR,
205 GPIOTE: p.GPIOTE,
206 PPI: p.PPI,
207 RADIO: p.RADIO,
208 RNG: p.RNG,
209 RTC0: p.RTC0,
210 TEMP: p.TEMP,
211 TIMER0: p.TIMER0,
212 TIMER1: p.TIMER1,
213 TIMER2: p.TIMER2,
214 TWI0: p.TWI0,
215 UART0: p.UART0,
216 }
217 }
218}
219
220/// Unused GPIO pins
221#[allow(missing_docs)]
222pub struct Pins {
223 // pub p0_00: p0::P0_00<Disconnected>, // SCL
224 // pub p0_01: p0::P0_01<Disconnected>, // PAD2, EDGE02
225 // pub p0_02: p0::P0_02<Disconnected>, // PAD1, EDGE01
226 // pub p0_03: p0::P0_03<Disconnected>, // PAD0, EDGE00
227 // pub p0_04: p0::P0_04<Disconnected>, // LEDs
228 // pub p0_05: p0::P0_05<Disconnected>, // LEDs
229 // pub p0_06: p0::P0_06<Disconnected>, // LEDs
230 // pub p0_07: p0::P0_07<Disconnected>, // LEDs
231 // pub p0_08: p0::P0_08<Disconnected>, // LEDs
232 // pub p0_09: p0::P0_09<Disconnected>, // LEDs
233 // pub p0_10: p0::P0_10<Disconnected>, // LEDs
234 // pub p0_11: p0::P0_11<Disconnected>, // LEDs
235 // pub p0_12: p0::P0_12<Disconnected>, // LEDs
236 // pub p0_13: p0::P0_13<Disconnected>, // LEDs
237 // pub p0_14: p0::P0_14<Disconnected>, // LEDs
238 // pub p0_15: p0::P0_15<Disconnected>, // LEDs
239 // pub p0_16: p0::P0_16<Disconnected>, // EDGE16
240 // pub p0_17: p0::P0_17<Disconnected>, // BTN_A
241 // pub p0_18: p0::P0_18<Disconnected>, // EDGE08
242 pub p0_19: p0::P0_19<Disconnected>,
243 // pub p0_20: p0::P0_20<Disconnected>, // EDGE12
244 pub p0_21: p0::P0_21<Disconnected>,
245 pub p0_22: p0::P0_22<Disconnected>,
246 pub p0_23: p0::P0_23<Disconnected>,
247 // pub p0_24: p0::P0_24<Disconnected>, // UART TX
248 // pub p0_25: p0::P0_25<Disconnected>, // UART RX
249 // pub p0_26: p0::P0_26<Disconnected>, // BTN_B
250 pub p0_27: p0::P0_27<Disconnected>,
251 pub p0_28: p0::P0_28<Disconnected>,
252 pub p0_29: p0::P0_29<Disconnected>,
253 // pub p0_30: p0::P0_30<Disconnected>, // SDA
254}
255
256/// Unused edge connector pins
257#[allow(missing_docs)]
258pub struct Edge {
259 // pub e03: COL1,
260 pub e00: EDGE00<Disconnected>, // <- big pad 1
261 // pub e04: COL2,
262 // pub e05: BTN_A,
263 // pub e06: COL9,
264 // pub e07: COL8,
265 pub e01: EDGE01<Disconnected>, // <- big pad 2
266 pub e08: EDGE08<Disconnected>,
267 // pub e09: COL7,
268 // pub e10: COL3,
269 // pub e11: BTN_B,
270 pub e12: EDGE12<Disconnected>,
271 pub e02: EDGE02<Disconnected>, // <- big pad 3
272 //pub e13<MODE>: SCK<MODE>,
273 //pub e14<MODE>: MISO<MODE>,
274 //pub e15<MODE>: MOSI<MODE>,
275 pub e16: EDGE16<Disconnected>,
276 // +V
277 // +V
278 // +V
279 // pub e19: SCL,
280 // pub e20: SDA,
281 // GND
282 // GND
283 // GND
284}
285
286/// Board buttons
287pub struct Buttons {
288 /// Left hand side button
289 pub button_a: BTN_A,
290 /// Right hand side button
291 pub button_b: BTN_B,
292}
293
294/// I2C shared internal and external bus pins
295pub struct I2CPins {
296 scl: SCL,
297 sda: SDA,
298}
299
300impl From<I2CPins> for twi::Pins {
301 fn from(pins: I2CPins) -> Self {
302 Self {
303 scl: pins.scl.degrade(),
304 sda: pins.sda.degrade(),
305 }
306 }
307}
308
309/// UART to debugger pins
310pub struct UartPins {
311 tx: UART_TX,
312 rx: UART_RX,
313}
314
315impl From<UartPins> for uart::Pins {
316 fn from(pins: UartPins) -> Self {
317 Self {
318 rxd: pins.rx.degrade(),
319 txd: pins.tx.degrade(),
320 cts: None,
321 rts: None,
322 }
323 }
324}