build_target/
arch.rs

1use crate::utils::{build_env, define_target_enum};
2use std::fmt;
3
4define_target_enum! {
5    /// Target CPU architecture
6    #[derive(Clone, Debug, Eq, Hash, PartialEq, PartialOrd, Ord)]
7    #[non_exhaustive]
8    pub enum Arch {
9        /// ARMv8 64-bit architecture
10        AArch64 => "aarch64",
11        /// AMD GPU architecture
12        Amdgpu => "amdgpu",
13        /// 32-bit ARM architecture
14        Arm => "arm",
15        /// ARM64 architecture with Windows EC (Emulation Compatible)
16        Arm64ec => "arm64ec",
17        /// AVR 8-bit microcontroller architecture
18        Avr => "avr",
19        /// Berkeley Packet Filter virtual machine architecture
20        Bpf => "bpf",
21        /// C-SKY CPU architecture
22        Csky => "csky",
23        /// Qualcomm Hexagon DSP architecture
24        Hexagon => "hexagon",
25        /// LoongArch 64-bit CPU architecture
26        Loongarch64 => "loongarch64",
27        /// Motorola 68k CPU architecture
28        M68k => "m68k",
29        /// 32-bit MIPS CPU architecture
30        Mips => "mips",
31        /// MIPS 32-bit Revision 6 architecture
32        Mips32r6 => "mips32r6",
33        /// 64-bit MIPS CPU architecture
34        Mips64 => "mips64",
35        /// MIPS 64-bit Revision 6 architecture
36        Mips64r6 => "mips64r6",
37        /// 16-bit MSP430 microcontroller architecture
38        Msp430 => "msp430",
39        /// 64-bit NVIDIA PTX virtual architecture
40        Nvptx64 => "nvptx64",
41        /// 32-bit POWERPC architecture
42        PowerPc => "powerpc",
43        /// 64-bit POWERPC architecture
44        PowerPc64 => "powerpc64",
45        /// 32-bit RISC-V architecture
46        Riscv32 => "riscv32",
47        /// 64-bit RISC-V architecture
48        Riscv64 => "riscv64",
49        /// 64-bit IBM mainframe architecture
50        S390X => "s390x",
51        /// 32-bit SPARC CPU architecture
52        Sparc => "sparc",
53        /// 64-bit SPARC CPU architecture
54        Sparc64 => "sparc64",
55        /// 32-bit WebAssembly architecture
56        Wasm32 => "wasm32",
57        /// 64-bit WebAssembly architecture
58        Wasm64 => "wasm64",
59        /// Generic 32-bit x86 CPU architecture
60        X86 => "x86",
61        /// 64-bit x86-64 (AMD64) CPU architecture
62        X86_64 => "x86_64",
63        /// Xtensa CPU architecture (commonly used in embedded systems)
64        Xtensa => "xtensa",
65    }
66
67    as_str_doc = "String representing this target architecture which matches `#[cfg(target_arch)]`.",
68    from_str_doc = "Tries to parse the given string as an [`Arch`] falling back to [`Arch::Other`] for unknown values.",
69}
70
71impl Arch {
72    /// Gets the current target [`Arch`].
73    #[must_use]
74    pub fn target() -> Self {
75        Self::from_str(build_env("CARGO_CFG_TARGET_ARCH"))
76    }
77}
78
79impl fmt::Display for Arch {
80    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
81        f.write_str(self.as_str())
82    }
83}
build_target/arch.rs

build_target/
arch.rs
