bl808_pac/glb/
uart_config.rs

1#[doc = "Register `uart_config` reader"]
2pub struct R(crate::R<UART_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_CONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_CONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_CONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `uart_config` writer"]
17pub struct W(crate::W<UART_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_CONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_CONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_CONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `clock_divide` reader - Peripheral clock divide factor"]
38pub type CLOCK_DIVIDE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `clock_divide` writer - Peripheral clock divide factor"]
40pub type CLOCK_DIVIDE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, UART_CONFIG_SPEC, u8, u8, 3, O>;
42#[doc = "Field `clock_enable` reader - Peripheral level clock gate enable"]
43pub type CLOCK_ENABLE_R = crate::BitReader<bool>;
44#[doc = "Field `clock_enable` writer - Peripheral level clock gate enable"]
45pub type CLOCK_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_CONFIG_SPEC, bool, O>;
46#[doc = "Field `hibernate_clock_source` reader - Reads clock source from hibernate registers"]
47pub type HIBERNATE_CLOCK_SOURCE_R = crate::BitReader<bool>;
48#[doc = "Field `hibernate_clock_source_2` reader - Reads clock source from hibernate registers"]
49pub type HIBERNATE_CLOCK_SOURCE_2_R = crate::BitReader<bool>;
50#[doc = "Field `uart2_mode` reader - Select interface mode for UART2 peripheral"]
51pub type UART2_MODE_R = crate::FieldReader<u8, UART2MODE_A>;
52#[doc = "Select interface mode for UART2 peripheral\n\nValue on reset: 0"]
53#[derive(Clone, Copy, Debug, PartialEq, Eq)]
54#[repr(u8)]
55pub enum UART2MODE_A {
56    #[doc = "0: Universal Asynchronous Receiver/Transmitter interface"]
57    UART = 0,
58    #[doc = "1: ISO 11898 communication protocol interface"]
59    ISO11898 = 1,
60}
61impl From<UART2MODE_A> for u8 {
62    #[inline(always)]
63    fn from(variant: UART2MODE_A) -> Self {
64        variant as _
65    }
66}
67impl UART2_MODE_R {
68    #[doc = "Get enumerated values variant"]
69    #[inline(always)]
70    pub fn variant(&self) -> Option<UART2MODE_A> {
71        match self.bits {
72            0 => Some(UART2MODE_A::UART),
73            1 => Some(UART2MODE_A::ISO11898),
74            _ => None,
75        }
76    }
77    #[doc = "Checks if the value of the field is `UART`"]
78    #[inline(always)]
79    pub fn is_uart(&self) -> bool {
80        *self == UART2MODE_A::UART
81    }
82    #[doc = "Checks if the value of the field is `ISO11898`"]
83    #[inline(always)]
84    pub fn is_iso11898(&self) -> bool {
85        *self == UART2MODE_A::ISO11898
86    }
87}
88#[doc = "Field `uart2_mode` writer - Select interface mode for UART2 peripheral"]
89pub type UART2_MODE_W<'a, const O: u8> =
90    crate::FieldWriter<'a, u32, UART_CONFIG_SPEC, u8, UART2MODE_A, 7, O>;
91impl<'a, const O: u8> UART2_MODE_W<'a, O> {
92    #[doc = "Universal Asynchronous Receiver/Transmitter interface"]
93    #[inline(always)]
94    pub fn uart(self) -> &'a mut W {
95        self.variant(UART2MODE_A::UART)
96    }
97    #[doc = "ISO 11898 communication protocol interface"]
98    #[inline(always)]
99    pub fn iso11898(self) -> &'a mut W {
100        self.variant(UART2MODE_A::ISO11898)
101    }
102}
103impl R {
104    #[doc = "Bits 0:2 - Peripheral clock divide factor"]
105    #[inline(always)]
106    pub fn clock_divide(&self) -> CLOCK_DIVIDE_R {
107        CLOCK_DIVIDE_R::new((self.bits & 7) as u8)
108    }
109    #[doc = "Bit 4 - Peripheral level clock gate enable"]
110    #[inline(always)]
111    pub fn clock_enable(&self) -> CLOCK_ENABLE_R {
112        CLOCK_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
113    }
114    #[doc = "Bit 7 - Reads clock source from hibernate registers"]
115    #[inline(always)]
116    pub fn hibernate_clock_source(&self) -> HIBERNATE_CLOCK_SOURCE_R {
117        HIBERNATE_CLOCK_SOURCE_R::new(((self.bits >> 7) & 1) != 0)
118    }
119    #[doc = "Bit 22 - Reads clock source from hibernate registers"]
120    #[inline(always)]
121    pub fn hibernate_clock_source_2(&self) -> HIBERNATE_CLOCK_SOURCE_2_R {
122        HIBERNATE_CLOCK_SOURCE_2_R::new(((self.bits >> 22) & 1) != 0)
123    }
124    #[doc = "Bits 25:31 - Select interface mode for UART2 peripheral"]
125    #[inline(always)]
126    pub fn uart2_mode(&self) -> UART2_MODE_R {
127        UART2_MODE_R::new(((self.bits >> 25) & 0x7f) as u8)
128    }
129}
130impl W {
131    #[doc = "Bits 0:2 - Peripheral clock divide factor"]
132    #[inline(always)]
133    pub fn clock_divide(&mut self) -> CLOCK_DIVIDE_W<0> {
134        CLOCK_DIVIDE_W::new(self)
135    }
136    #[doc = "Bit 4 - Peripheral level clock gate enable"]
137    #[inline(always)]
138    pub fn clock_enable(&mut self) -> CLOCK_ENABLE_W<4> {
139        CLOCK_ENABLE_W::new(self)
140    }
141    #[doc = "Bits 25:31 - Select interface mode for UART2 peripheral"]
142    #[inline(always)]
143    pub fn uart2_mode(&mut self) -> UART2_MODE_W<25> {
144        UART2_MODE_W::new(self)
145    }
146    #[doc = "Writes raw bits to the register."]
147    #[inline(always)]
148    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
149        self.0.bits(bits);
150        self
151    }
152}
153#[doc = "Universal Asynchronous Receiver/Transmitter configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_config](index.html) module"]
154pub struct UART_CONFIG_SPEC;
155impl crate::RegisterSpec for UART_CONFIG_SPEC {
156    type Ux = u32;
157}
158#[doc = "`read()` method returns [uart_config::R](R) reader structure"]
159impl crate::Readable for UART_CONFIG_SPEC {
160    type Reader = R;
161}
162#[doc = "`write(|w| ..)` method takes [uart_config::W](W) writer structure"]
163impl crate::Writable for UART_CONFIG_SPEC {
164    type Writer = W;
165}
166#[doc = "`reset()` method sets uart_config to value 0"]
167impl crate::Resettable for UART_CONFIG_SPEC {
168    #[inline(always)]
169    fn reset_value() -> Self::Ux {
170        0
171    }
172}
bl808_pac/glb/uart_config.rs

bl808_pac/glb/
uart_config.rs
