bl808_pac/i2s/
fifo_config_0.rs

1#[doc = "Register `fifo_config_0` reader"]
2pub struct R(crate::R<FIFO_CONFIG_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FIFO_CONFIG_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FIFO_CONFIG_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FIFO_CONFIG_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `fifo_config_0` writer"]
17pub struct W(crate::W<FIFO_CONFIG_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FIFO_CONFIG_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FIFO_CONFIG_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FIFO_CONFIG_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `transmit_dma` reader - Enable signal of transmit DMA interface"]
38pub use RECEIVE_DMA_R as TRANSMIT_DMA_R;
39#[doc = "Field `transmit_dma` writer - Enable signal of transmit DMA interface"]
40pub use RECEIVE_DMA_W as TRANSMIT_DMA_W;
41#[doc = "Field `receive_dma` reader - Enable signal of receive DMA interface"]
42pub type RECEIVE_DMA_R = crate::BitReader<DMA_ENABLE_A>;
43#[doc = "Enable signal of receive DMA interface\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum DMA_ENABLE_A {
46    #[doc = "1: Enable DMA interface"]
47    ENABLE = 1,
48    #[doc = "0: Disable DMA interface"]
49    DISABLE = 0,
50}
51impl From<DMA_ENABLE_A> for bool {
52    #[inline(always)]
53    fn from(variant: DMA_ENABLE_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl RECEIVE_DMA_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> DMA_ENABLE_A {
61        match self.bits {
62            true => DMA_ENABLE_A::ENABLE,
63            false => DMA_ENABLE_A::DISABLE,
64        }
65    }
66    #[doc = "Checks if the value of the field is `ENABLE`"]
67    #[inline(always)]
68    pub fn is_enable(&self) -> bool {
69        *self == DMA_ENABLE_A::ENABLE
70    }
71    #[doc = "Checks if the value of the field is `DISABLE`"]
72    #[inline(always)]
73    pub fn is_disable(&self) -> bool {
74        *self == DMA_ENABLE_A::DISABLE
75    }
76}
77#[doc = "Field `receive_dma` writer - Enable signal of receive DMA interface"]
78pub type RECEIVE_DMA_W<'a, const O: u8> =
79    crate::BitWriter<'a, u32, FIFO_CONFIG_0_SPEC, DMA_ENABLE_A, O>;
80impl<'a, const O: u8> RECEIVE_DMA_W<'a, O> {
81    #[doc = "Enable DMA interface"]
82    #[inline(always)]
83    pub fn enable(self) -> &'a mut W {
84        self.variant(DMA_ENABLE_A::ENABLE)
85    }
86    #[doc = "Disable DMA interface"]
87    #[inline(always)]
88    pub fn disable(self) -> &'a mut W {
89        self.variant(DMA_ENABLE_A::DISABLE)
90    }
91}
92#[doc = "Field `transmit_clear` writer - Clears transmit FIFO overflow and underflow flags"]
93pub use RECEIVE_CLEAR_W as TRANSMIT_CLEAR_W;
94#[doc = "Clears receive FIFO overflow and underflow flags\n\nValue on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum FLAG_CLEAR_AW {
97    #[doc = "1: Write 1 to clear fifo flags"]
98    CLEAR = 1,
99}
100impl From<FLAG_CLEAR_AW> for bool {
101    #[inline(always)]
102    fn from(variant: FLAG_CLEAR_AW) -> Self {
103        variant as u8 != 0
104    }
105}
106#[doc = "Field `receive_clear` writer - Clears receive FIFO overflow and underflow flags"]
107pub type RECEIVE_CLEAR_W<'a, const O: u8> =
108    crate::BitWriter<'a, u32, FIFO_CONFIG_0_SPEC, FLAG_CLEAR_AW, O>;
109impl<'a, const O: u8> RECEIVE_CLEAR_W<'a, O> {
110    #[doc = "Write 1 to clear fifo flags"]
111    #[inline(always)]
112    pub fn clear(self) -> &'a mut W {
113        self.variant(FLAG_CLEAR_AW::CLEAR)
114    }
115}
116#[doc = "Field `transmit_overflow` reader - Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`."]
117pub use RECEIVE_OVERFLOW_R as TRANSMIT_OVERFLOW_R;
118#[doc = "Field `transmit_underflow` reader - Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`."]
119pub use RECEIVE_UNDERFLOW_R as TRANSMIT_UNDERFLOW_R;
120#[doc = "Field `receive_overflow` reader - Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`."]
121pub type RECEIVE_OVERFLOW_R = crate::BitReader<HAS_OVERFLOW_A>;
122#[doc = "Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`.\n\nValue on reset: 0"]
123#[derive(Clone, Copy, Debug, PartialEq, Eq)]
124pub enum HAS_OVERFLOW_A {
125    #[doc = "0: No FIFO buffer overflow"]
126    NOT_OVERFLOW = 0,
127    #[doc = "1: Has FIFO buffer overflow"]
128    OVERFLOW = 1,
129}
130impl From<HAS_OVERFLOW_A> for bool {
131    #[inline(always)]
132    fn from(variant: HAS_OVERFLOW_A) -> Self {
133        variant as u8 != 0
134    }
135}
136impl RECEIVE_OVERFLOW_R {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub fn variant(&self) -> HAS_OVERFLOW_A {
140        match self.bits {
141            false => HAS_OVERFLOW_A::NOT_OVERFLOW,
142            true => HAS_OVERFLOW_A::OVERFLOW,
143        }
144    }
145    #[doc = "Checks if the value of the field is `NOT_OVERFLOW`"]
146    #[inline(always)]
147    pub fn is_not_overflow(&self) -> bool {
148        *self == HAS_OVERFLOW_A::NOT_OVERFLOW
149    }
150    #[doc = "Checks if the value of the field is `OVERFLOW`"]
151    #[inline(always)]
152    pub fn is_overflow(&self) -> bool {
153        *self == HAS_OVERFLOW_A::OVERFLOW
154    }
155}
156#[doc = "Field `receive_underflow` reader - Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`."]
157pub type RECEIVE_UNDERFLOW_R = crate::BitReader<HAS_UNDERFLOW_A>;
158#[doc = "Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`.\n\nValue on reset: 0"]
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160pub enum HAS_UNDERFLOW_A {
161    #[doc = "0: No FIFO buffer underflow"]
162    NOT_UNDERFLOW = 0,
163    #[doc = "1: Has FIFO buffer underflow"]
164    UNDERFLOW = 1,
165}
166impl From<HAS_UNDERFLOW_A> for bool {
167    #[inline(always)]
168    fn from(variant: HAS_UNDERFLOW_A) -> Self {
169        variant as u8 != 0
170    }
171}
172impl RECEIVE_UNDERFLOW_R {
173    #[doc = "Get enumerated values variant"]
174    #[inline(always)]
175    pub fn variant(&self) -> HAS_UNDERFLOW_A {
176        match self.bits {
177            false => HAS_UNDERFLOW_A::NOT_UNDERFLOW,
178            true => HAS_UNDERFLOW_A::UNDERFLOW,
179        }
180    }
181    #[doc = "Checks if the value of the field is `NOT_UNDERFLOW`"]
182    #[inline(always)]
183    pub fn is_not_underflow(&self) -> bool {
184        *self == HAS_UNDERFLOW_A::NOT_UNDERFLOW
185    }
186    #[doc = "Checks if the value of the field is `UNDERFLOW`"]
187    #[inline(always)]
188    pub fn is_underflow(&self) -> bool {
189        *self == HAS_UNDERFLOW_A::UNDERFLOW
190    }
191}
192#[doc = "Field `merge_left_right` reader - "]
193pub type MERGE_LEFT_RIGHT_R = crate::BitReader<bool>;
194#[doc = "Field `merge_left_right` writer - "]
195pub type MERGE_LEFT_RIGHT_W<'a, const O: u8> =
196    crate::BitWriter<'a, u32, FIFO_CONFIG_0_SPEC, bool, O>;
197#[doc = "Field `swap_left_right` reader - "]
198pub type SWAP_LEFT_RIGHT_R = crate::BitReader<bool>;
199#[doc = "Field `swap_left_right` writer - "]
200pub type SWAP_LEFT_RIGHT_W<'a, const O: u8> =
201    crate::BitWriter<'a, u32, FIFO_CONFIG_0_SPEC, bool, O>;
202#[doc = "Field `left_justified` reader - "]
203pub type LEFT_JUSTIFIED_R = crate::BitReader<bool>;
204#[doc = "Field `left_justified` writer - "]
205pub type LEFT_JUSTIFIED_W<'a, const O: u8> = crate::BitWriter<'a, u32, FIFO_CONFIG_0_SPEC, bool, O>;
206impl R {
207    #[doc = "Bit 0 - Enable signal of transmit DMA interface"]
208    #[inline(always)]
209    pub fn transmit_dma(&self) -> TRANSMIT_DMA_R {
210        TRANSMIT_DMA_R::new((self.bits & 1) != 0)
211    }
212    #[doc = "Bit 1 - Enable signal of receive DMA interface"]
213    #[inline(always)]
214    pub fn receive_dma(&self) -> RECEIVE_DMA_R {
215        RECEIVE_DMA_R::new(((self.bits >> 1) & 1) != 0)
216    }
217    #[doc = "Bit 4 - Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`."]
218    #[inline(always)]
219    pub fn transmit_overflow(&self) -> TRANSMIT_OVERFLOW_R {
220        TRANSMIT_OVERFLOW_R::new(((self.bits >> 4) & 1) != 0)
221    }
222    #[doc = "Bit 5 - Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`."]
223    #[inline(always)]
224    pub fn transmit_underflow(&self) -> TRANSMIT_UNDERFLOW_R {
225        TRANSMIT_UNDERFLOW_R::new(((self.bits >> 5) & 1) != 0)
226    }
227    #[doc = "Bit 6 - Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`."]
228    #[inline(always)]
229    pub fn receive_overflow(&self) -> RECEIVE_OVERFLOW_R {
230        RECEIVE_OVERFLOW_R::new(((self.bits >> 6) & 1) != 0)
231    }
232    #[doc = "Bit 7 - Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`."]
233    #[inline(always)]
234    pub fn receive_underflow(&self) -> RECEIVE_UNDERFLOW_R {
235        RECEIVE_UNDERFLOW_R::new(((self.bits >> 7) & 1) != 0)
236    }
237    #[doc = "Bit 8"]
238    #[inline(always)]
239    pub fn merge_left_right(&self) -> MERGE_LEFT_RIGHT_R {
240        MERGE_LEFT_RIGHT_R::new(((self.bits >> 8) & 1) != 0)
241    }
242    #[doc = "Bit 9"]
243    #[inline(always)]
244    pub fn swap_left_right(&self) -> SWAP_LEFT_RIGHT_R {
245        SWAP_LEFT_RIGHT_R::new(((self.bits >> 9) & 1) != 0)
246    }
247    #[doc = "Bit 10"]
248    #[inline(always)]
249    pub fn left_justified(&self) -> LEFT_JUSTIFIED_R {
250        LEFT_JUSTIFIED_R::new(((self.bits >> 10) & 1) != 0)
251    }
252}
253impl W {
254    #[doc = "Bit 0 - Enable signal of transmit DMA interface"]
255    #[inline(always)]
256    pub fn transmit_dma(&mut self) -> TRANSMIT_DMA_W<0> {
257        TRANSMIT_DMA_W::new(self)
258    }
259    #[doc = "Bit 1 - Enable signal of receive DMA interface"]
260    #[inline(always)]
261    pub fn receive_dma(&mut self) -> RECEIVE_DMA_W<1> {
262        RECEIVE_DMA_W::new(self)
263    }
264    #[doc = "Bit 2 - Clears transmit FIFO overflow and underflow flags"]
265    #[inline(always)]
266    pub fn transmit_clear(&mut self) -> TRANSMIT_CLEAR_W<2> {
267        TRANSMIT_CLEAR_W::new(self)
268    }
269    #[doc = "Bit 3 - Clears receive FIFO overflow and underflow flags"]
270    #[inline(always)]
271    pub fn receive_clear(&mut self) -> RECEIVE_CLEAR_W<3> {
272        RECEIVE_CLEAR_W::new(self)
273    }
274    #[doc = "Bit 8"]
275    #[inline(always)]
276    pub fn merge_left_right(&mut self) -> MERGE_LEFT_RIGHT_W<8> {
277        MERGE_LEFT_RIGHT_W::new(self)
278    }
279    #[doc = "Bit 9"]
280    #[inline(always)]
281    pub fn swap_left_right(&mut self) -> SWAP_LEFT_RIGHT_W<9> {
282        SWAP_LEFT_RIGHT_W::new(self)
283    }
284    #[doc = "Bit 10"]
285    #[inline(always)]
286    pub fn left_justified(&mut self) -> LEFT_JUSTIFIED_W<10> {
287        LEFT_JUSTIFIED_W::new(self)
288    }
289    #[doc = "Writes raw bits to the register."]
290    #[inline(always)]
291    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
292        self.0.bits(bits);
293        self
294    }
295}
296#[doc = "FIFO configuration register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_config_0](index.html) module"]
297pub struct FIFO_CONFIG_0_SPEC;
298impl crate::RegisterSpec for FIFO_CONFIG_0_SPEC {
299    type Ux = u32;
300}
301#[doc = "`read()` method returns [fifo_config_0::R](R) reader structure"]
302impl crate::Readable for FIFO_CONFIG_0_SPEC {
303    type Reader = R;
304}
305#[doc = "`write(|w| ..)` method takes [fifo_config_0::W](W) writer structure"]
306impl crate::Writable for FIFO_CONFIG_0_SPEC {
307    type Writer = W;
308}
309#[doc = "`reset()` method sets fifo_config_0 to value 0"]
310impl crate::Resettable for FIFO_CONFIG_0_SPEC {
311    #[inline(always)]
312    fn reset_value() -> Self::Ux {
313        0
314    }
315}
bl808_pac/i2s/fifo_config_0.rs

bl808_pac/i2s/
fifo_config_0.rs
