1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Interface enables and configurations"]
5 pub mode: MODE,
6 #[doc = "0x04 - Interrupt source register"]
7 pub interrupt_source: INTERRUPT_SOURCE,
8 #[doc = "0x08 - Interrupt mask register"]
9 pub interrupt_mask: INTERRUPT_MASK,
10 #[doc = "0x0c - Back-to-back inter-packet gap register"]
11 pub backed_gap: BACKED_GAP,
12 #[doc = "0x10 - Non back-to-back inter-packet gap register 1"]
13 pub non_backed_gap_1: NON_BACKED_GAP_1,
14 #[doc = "0x14 - Non back-to-back inter-packet gap register 2"]
15 pub non_backed_gap_2: NON_BACKED_GAP_2,
16 #[doc = "0x18 - Minimum and maximum ethernet frame length"]
17 pub frame_length: FRAME_LENGTH,
18 #[doc = "0x1c - Collision time window and maximum retries"]
19 pub collision: COLLISION,
20 #[doc = "0x20 - Transmit buffer descriptor"]
21 pub transmit_buffer: TRANSMIT_BUFFER,
22 #[doc = "0x24 - Control frame function register"]
23 pub flow_control: FLOW_CONTROL,
24 #[doc = "0x28 - MII clock divider and premable enable"]
25 pub mii_mode: MII_MODE,
26 #[doc = "0x2c - MII control data, read and scan state"]
27 pub mii_command: MII_COMMAND,
28 #[doc = "0x30 - Physical layer bus address"]
29 pub mii_address: MII_ADDRESS,
30 #[doc = "0x34 - Write data to MII physcial layer"]
31 pub control_write: CONTROL_WRITE,
32 #[doc = "0x38 - Read data from MII physcial layer"]
33 pub control_read: CONTROL_READ,
34 #[doc = "0x3c - MII bus and link layer state"]
35 pub mii_state: MII_STATE,
36 #[doc = "0x40..0x48 - Media Access Control address"]
37 pub mac_address: [MAC_ADDRESS; 2],
38 #[doc = "0x48..0x50 - Hash register"]
39 pub hash: [HASH; 2],
40 #[doc = "0x50 - Transmit control register"]
41 pub transmit_control: TRANSMIT_CONTROL,
42}
43#[doc = "mode (rw) register accessor: an alias for `Reg<MODE_SPEC>`"]
44pub type MODE = crate::Reg<mode::MODE_SPEC>;
45#[doc = "Interface enables and configurations"]
46pub mod mode;
47#[doc = "interrupt_source (rw) register accessor: an alias for `Reg<INTERRUPT_SOURCE_SPEC>`"]
48pub type INTERRUPT_SOURCE = crate::Reg<interrupt_source::INTERRUPT_SOURCE_SPEC>;
49#[doc = "Interrupt source register"]
50pub mod interrupt_source;
51#[doc = "interrupt_mask (rw) register accessor: an alias for `Reg<INTERRUPT_MASK_SPEC>`"]
52pub type INTERRUPT_MASK = crate::Reg<interrupt_mask::INTERRUPT_MASK_SPEC>;
53#[doc = "Interrupt mask register"]
54pub mod interrupt_mask;
55#[doc = "backed_gap (rw) register accessor: an alias for `Reg<BACKED_GAP_SPEC>`"]
56pub type BACKED_GAP = crate::Reg<backed_gap::BACKED_GAP_SPEC>;
57#[doc = "Back-to-back inter-packet gap register"]
58pub mod backed_gap;
59#[doc = "non_backed_gap_1 (rw) register accessor: an alias for `Reg<NON_BACKED_GAP_1_SPEC>`"]
60pub type NON_BACKED_GAP_1 = crate::Reg<non_backed_gap_1::NON_BACKED_GAP_1_SPEC>;
61#[doc = "Non back-to-back inter-packet gap register 1"]
62pub mod non_backed_gap_1;
63#[doc = "non_backed_gap_2 (rw) register accessor: an alias for `Reg<NON_BACKED_GAP_2_SPEC>`"]
64pub type NON_BACKED_GAP_2 = crate::Reg<non_backed_gap_2::NON_BACKED_GAP_2_SPEC>;
65#[doc = "Non back-to-back inter-packet gap register 2"]
66pub mod non_backed_gap_2;
67#[doc = "frame_length (rw) register accessor: an alias for `Reg<FRAME_LENGTH_SPEC>`"]
68pub type FRAME_LENGTH = crate::Reg<frame_length::FRAME_LENGTH_SPEC>;
69#[doc = "Minimum and maximum ethernet frame length"]
70pub mod frame_length;
71#[doc = "collision (rw) register accessor: an alias for `Reg<COLLISION_SPEC>`"]
72pub type COLLISION = crate::Reg<collision::COLLISION_SPEC>;
73#[doc = "Collision time window and maximum retries"]
74pub mod collision;
75#[doc = "transmit_buffer (rw) register accessor: an alias for `Reg<TRANSMIT_BUFFER_SPEC>`"]
76pub type TRANSMIT_BUFFER = crate::Reg<transmit_buffer::TRANSMIT_BUFFER_SPEC>;
77#[doc = "Transmit buffer descriptor"]
78pub mod transmit_buffer;
79#[doc = "flow_control (rw) register accessor: an alias for `Reg<FLOW_CONTROL_SPEC>`"]
80pub type FLOW_CONTROL = crate::Reg<flow_control::FLOW_CONTROL_SPEC>;
81#[doc = "Control frame function register"]
82pub mod flow_control;
83#[doc = "mii_mode (rw) register accessor: an alias for `Reg<MII_MODE_SPEC>`"]
84pub type MII_MODE = crate::Reg<mii_mode::MII_MODE_SPEC>;
85#[doc = "MII clock divider and premable enable"]
86pub mod mii_mode;
87#[doc = "mii_command (rw) register accessor: an alias for `Reg<MII_COMMAND_SPEC>`"]
88pub type MII_COMMAND = crate::Reg<mii_command::MII_COMMAND_SPEC>;
89#[doc = "MII control data, read and scan state"]
90pub mod mii_command;
91#[doc = "mii_address (rw) register accessor: an alias for `Reg<MII_ADDRESS_SPEC>`"]
92pub type MII_ADDRESS = crate::Reg<mii_address::MII_ADDRESS_SPEC>;
93#[doc = "Physical layer bus address"]
94pub mod mii_address;
95#[doc = "control_write (rw) register accessor: an alias for `Reg<CONTROL_WRITE_SPEC>`"]
96pub type CONTROL_WRITE = crate::Reg<control_write::CONTROL_WRITE_SPEC>;
97#[doc = "Write data to MII physcial layer"]
98pub mod control_write;
99#[doc = "control_read (rw) register accessor: an alias for `Reg<CONTROL_READ_SPEC>`"]
100pub type CONTROL_READ = crate::Reg<control_read::CONTROL_READ_SPEC>;
101#[doc = "Read data from MII physcial layer"]
102pub mod control_read;
103#[doc = "mii_state (rw) register accessor: an alias for `Reg<MII_STATE_SPEC>`"]
104pub type MII_STATE = crate::Reg<mii_state::MII_STATE_SPEC>;
105#[doc = "MII bus and link layer state"]
106pub mod mii_state;
107#[doc = "mac_address (rw) register accessor: an alias for `Reg<MAC_ADDRESS_SPEC>`"]
108pub type MAC_ADDRESS = crate::Reg<mac_address::MAC_ADDRESS_SPEC>;
109#[doc = "Media Access Control address"]
110pub mod mac_address;
111#[doc = "hash (rw) register accessor: an alias for `Reg<HASH_SPEC>`"]
112pub type HASH = crate::Reg<hash::HASH_SPEC>;
113#[doc = "Hash register"]
114pub mod hash;
115#[doc = "transmit_control (rw) register accessor: an alias for `Reg<TRANSMIT_CONTROL_SPEC>`"]
116pub type TRANSMIT_CONTROL = crate::Reg<transmit_control::TRANSMIT_CONTROL_SPEC>;
117#[doc = "Transmit control register"]
118pub mod transmit_control;