bl702_pac/uart/
uart_int_sts.rs

1#[doc = "Register `uart_int_sts` reader"]
2pub struct R(crate::R<UART_INT_STS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_INT_STS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_INT_STS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_INT_STS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `uart_int_sts` writer"]
17pub struct W(crate::W<UART_INT_STS_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_INT_STS_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_INT_STS_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_INT_STS_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `utx_end_int` reader - "]
38pub type UTX_END_INT_R = crate::BitReader<bool>;
39#[doc = "Field `utx_end_int` writer - "]
40pub type UTX_END_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
41#[doc = "Field `urx_end_int` reader - "]
42pub type URX_END_INT_R = crate::BitReader<bool>;
43#[doc = "Field `urx_end_int` writer - "]
44pub type URX_END_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
45#[doc = "Field `utx_fifo_int` reader - "]
46pub type UTX_FIFO_INT_R = crate::BitReader<bool>;
47#[doc = "Field `utx_fifo_int` writer - "]
48pub type UTX_FIFO_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
49#[doc = "Field `urx_fifo_int` reader - "]
50pub type URX_FIFO_INT_R = crate::BitReader<bool>;
51#[doc = "Field `urx_fifo_int` writer - "]
52pub type URX_FIFO_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
53#[doc = "Field `urx_rto_int` reader - "]
54pub type URX_RTO_INT_R = crate::BitReader<bool>;
55#[doc = "Field `urx_rto_int` writer - "]
56pub type URX_RTO_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
57#[doc = "Field `urx_pce_int` reader - "]
58pub type URX_PCE_INT_R = crate::BitReader<bool>;
59#[doc = "Field `urx_pce_int` writer - "]
60pub type URX_PCE_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
61#[doc = "Field `utx_fer_int` reader - "]
62pub type UTX_FER_INT_R = crate::BitReader<bool>;
63#[doc = "Field `utx_fer_int` writer - "]
64pub type UTX_FER_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
65#[doc = "Field `urx_fer_int` reader - "]
66pub type URX_FER_INT_R = crate::BitReader<bool>;
67#[doc = "Field `urx_fer_int` writer - "]
68pub type URX_FER_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
69#[doc = "Field `urx_lse_int` reader - "]
70pub type URX_LSE_INT_R = crate::BitReader<bool>;
71#[doc = "Field `urx_lse_int` writer - "]
72pub type URX_LSE_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_STS_SPEC, bool, O>;
73impl R {
74    #[doc = "Bit 0"]
75    #[inline(always)]
76    pub fn utx_end_int(&self) -> UTX_END_INT_R {
77        UTX_END_INT_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1"]
80    #[inline(always)]
81    pub fn urx_end_int(&self) -> URX_END_INT_R {
82        URX_END_INT_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2"]
85    #[inline(always)]
86    pub fn utx_fifo_int(&self) -> UTX_FIFO_INT_R {
87        UTX_FIFO_INT_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3"]
90    #[inline(always)]
91    pub fn urx_fifo_int(&self) -> URX_FIFO_INT_R {
92        URX_FIFO_INT_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 4"]
95    #[inline(always)]
96    pub fn urx_rto_int(&self) -> URX_RTO_INT_R {
97        URX_RTO_INT_R::new(((self.bits >> 4) & 1) != 0)
98    }
99    #[doc = "Bit 5"]
100    #[inline(always)]
101    pub fn urx_pce_int(&self) -> URX_PCE_INT_R {
102        URX_PCE_INT_R::new(((self.bits >> 5) & 1) != 0)
103    }
104    #[doc = "Bit 6"]
105    #[inline(always)]
106    pub fn utx_fer_int(&self) -> UTX_FER_INT_R {
107        UTX_FER_INT_R::new(((self.bits >> 6) & 1) != 0)
108    }
109    #[doc = "Bit 7"]
110    #[inline(always)]
111    pub fn urx_fer_int(&self) -> URX_FER_INT_R {
112        URX_FER_INT_R::new(((self.bits >> 7) & 1) != 0)
113    }
114    #[doc = "Bit 8"]
115    #[inline(always)]
116    pub fn urx_lse_int(&self) -> URX_LSE_INT_R {
117        URX_LSE_INT_R::new(((self.bits >> 8) & 1) != 0)
118    }
119}
120impl W {
121    #[doc = "Bit 0"]
122    #[inline(always)]
123    #[must_use]
124    pub fn utx_end_int(&mut self) -> UTX_END_INT_W<0> {
125        UTX_END_INT_W::new(self)
126    }
127    #[doc = "Bit 1"]
128    #[inline(always)]
129    #[must_use]
130    pub fn urx_end_int(&mut self) -> URX_END_INT_W<1> {
131        URX_END_INT_W::new(self)
132    }
133    #[doc = "Bit 2"]
134    #[inline(always)]
135    #[must_use]
136    pub fn utx_fifo_int(&mut self) -> UTX_FIFO_INT_W<2> {
137        UTX_FIFO_INT_W::new(self)
138    }
139    #[doc = "Bit 3"]
140    #[inline(always)]
141    #[must_use]
142    pub fn urx_fifo_int(&mut self) -> URX_FIFO_INT_W<3> {
143        URX_FIFO_INT_W::new(self)
144    }
145    #[doc = "Bit 4"]
146    #[inline(always)]
147    #[must_use]
148    pub fn urx_rto_int(&mut self) -> URX_RTO_INT_W<4> {
149        URX_RTO_INT_W::new(self)
150    }
151    #[doc = "Bit 5"]
152    #[inline(always)]
153    #[must_use]
154    pub fn urx_pce_int(&mut self) -> URX_PCE_INT_W<5> {
155        URX_PCE_INT_W::new(self)
156    }
157    #[doc = "Bit 6"]
158    #[inline(always)]
159    #[must_use]
160    pub fn utx_fer_int(&mut self) -> UTX_FER_INT_W<6> {
161        UTX_FER_INT_W::new(self)
162    }
163    #[doc = "Bit 7"]
164    #[inline(always)]
165    #[must_use]
166    pub fn urx_fer_int(&mut self) -> URX_FER_INT_W<7> {
167        URX_FER_INT_W::new(self)
168    }
169    #[doc = "Bit 8"]
170    #[inline(always)]
171    #[must_use]
172    pub fn urx_lse_int(&mut self) -> URX_LSE_INT_W<8> {
173        URX_LSE_INT_W::new(self)
174    }
175    #[doc = "Writes raw bits to the register."]
176    #[inline(always)]
177    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
178        self.0.bits(bits);
179        self
180    }
181}
182#[doc = "UART interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_sts](index.html) module"]
183pub struct UART_INT_STS_SPEC;
184impl crate::RegisterSpec for UART_INT_STS_SPEC {
185    type Ux = u32;
186}
187#[doc = "`read()` method returns [uart_int_sts::R](R) reader structure"]
188impl crate::Readable for UART_INT_STS_SPEC {
189    type Reader = R;
190}
191#[doc = "`write(|w| ..)` method takes [uart_int_sts::W](W) writer structure"]
192impl crate::Writable for UART_INT_STS_SPEC {
193    type Writer = W;
194    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196}
197#[doc = "`reset()` method sets uart_int_sts to value 0"]
198impl crate::Resettable for UART_INT_STS_SPEC {
199    const RESET_VALUE: Self::Ux = 0;
200}
bl702_pac/uart/uart_int_sts.rs

bl702_pac/uart/
uart_int_sts.rs
