bl702_pac/uart/
uart_int_clear.rs

1#[doc = "Register `uart_int_clear` reader"]
2pub struct R(crate::R<UART_INT_CLEAR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_INT_CLEAR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_INT_CLEAR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_INT_CLEAR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `uart_int_clear` writer"]
17pub struct W(crate::W<UART_INT_CLEAR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_INT_CLEAR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_INT_CLEAR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_INT_CLEAR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `cr_utx_end_clr` reader - "]
38pub type CR_UTX_END_CLR_R = crate::BitReader<bool>;
39#[doc = "Field `cr_utx_end_clr` writer - "]
40pub type CR_UTX_END_CLR_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
42#[doc = "Field `cr_urx_end_clr` reader - "]
43pub type CR_URX_END_CLR_R = crate::BitReader<bool>;
44#[doc = "Field `cr_urx_end_clr` writer - "]
45pub type CR_URX_END_CLR_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
47#[doc = "Field `rsvd_2` reader - "]
48pub type RSVD_2_R = crate::BitReader<bool>;
49#[doc = "Field `rsvd_2` writer - "]
50pub type RSVD_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
51#[doc = "Field `rsvd_3` reader - "]
52pub type RSVD_3_R = crate::BitReader<bool>;
53#[doc = "Field `rsvd_3` writer - "]
54pub type RSVD_3_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
55#[doc = "Field `cr_urx_rto_clr` reader - "]
56pub type CR_URX_RTO_CLR_R = crate::BitReader<bool>;
57#[doc = "Field `cr_urx_rto_clr` writer - "]
58pub type CR_URX_RTO_CLR_W<'a, const O: u8> =
59    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
60#[doc = "Field `cr_urx_pce_clr` reader - "]
61pub type CR_URX_PCE_CLR_R = crate::BitReader<bool>;
62#[doc = "Field `cr_urx_pce_clr` writer - "]
63pub type CR_URX_PCE_CLR_W<'a, const O: u8> =
64    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
65#[doc = "Field `rsvd_6` reader - "]
66pub type RSVD_6_R = crate::BitReader<bool>;
67#[doc = "Field `rsvd_6` writer - "]
68pub type RSVD_6_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
69#[doc = "Field `rsvd_7` reader - "]
70pub type RSVD_7_R = crate::BitReader<bool>;
71#[doc = "Field `rsvd_7` writer - "]
72pub type RSVD_7_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
73#[doc = "Field `cr_urx_lse_clr` reader - "]
74pub type CR_URX_LSE_CLR_R = crate::BitReader<bool>;
75#[doc = "Field `cr_urx_lse_clr` writer - "]
76pub type CR_URX_LSE_CLR_W<'a, const O: u8> =
77    crate::BitWriter<'a, u32, UART_INT_CLEAR_SPEC, bool, O>;
78impl R {
79    #[doc = "Bit 0"]
80    #[inline(always)]
81    pub fn cr_utx_end_clr(&self) -> CR_UTX_END_CLR_R {
82        CR_UTX_END_CLR_R::new((self.bits & 1) != 0)
83    }
84    #[doc = "Bit 1"]
85    #[inline(always)]
86    pub fn cr_urx_end_clr(&self) -> CR_URX_END_CLR_R {
87        CR_URX_END_CLR_R::new(((self.bits >> 1) & 1) != 0)
88    }
89    #[doc = "Bit 2"]
90    #[inline(always)]
91    pub fn rsvd_2(&self) -> RSVD_2_R {
92        RSVD_2_R::new(((self.bits >> 2) & 1) != 0)
93    }
94    #[doc = "Bit 3"]
95    #[inline(always)]
96    pub fn rsvd_3(&self) -> RSVD_3_R {
97        RSVD_3_R::new(((self.bits >> 3) & 1) != 0)
98    }
99    #[doc = "Bit 4"]
100    #[inline(always)]
101    pub fn cr_urx_rto_clr(&self) -> CR_URX_RTO_CLR_R {
102        CR_URX_RTO_CLR_R::new(((self.bits >> 4) & 1) != 0)
103    }
104    #[doc = "Bit 5"]
105    #[inline(always)]
106    pub fn cr_urx_pce_clr(&self) -> CR_URX_PCE_CLR_R {
107        CR_URX_PCE_CLR_R::new(((self.bits >> 5) & 1) != 0)
108    }
109    #[doc = "Bit 6"]
110    #[inline(always)]
111    pub fn rsvd_6(&self) -> RSVD_6_R {
112        RSVD_6_R::new(((self.bits >> 6) & 1) != 0)
113    }
114    #[doc = "Bit 7"]
115    #[inline(always)]
116    pub fn rsvd_7(&self) -> RSVD_7_R {
117        RSVD_7_R::new(((self.bits >> 7) & 1) != 0)
118    }
119    #[doc = "Bit 8"]
120    #[inline(always)]
121    pub fn cr_urx_lse_clr(&self) -> CR_URX_LSE_CLR_R {
122        CR_URX_LSE_CLR_R::new(((self.bits >> 8) & 1) != 0)
123    }
124}
125impl W {
126    #[doc = "Bit 0"]
127    #[inline(always)]
128    #[must_use]
129    pub fn cr_utx_end_clr(&mut self) -> CR_UTX_END_CLR_W<0> {
130        CR_UTX_END_CLR_W::new(self)
131    }
132    #[doc = "Bit 1"]
133    #[inline(always)]
134    #[must_use]
135    pub fn cr_urx_end_clr(&mut self) -> CR_URX_END_CLR_W<1> {
136        CR_URX_END_CLR_W::new(self)
137    }
138    #[doc = "Bit 2"]
139    #[inline(always)]
140    #[must_use]
141    pub fn rsvd_2(&mut self) -> RSVD_2_W<2> {
142        RSVD_2_W::new(self)
143    }
144    #[doc = "Bit 3"]
145    #[inline(always)]
146    #[must_use]
147    pub fn rsvd_3(&mut self) -> RSVD_3_W<3> {
148        RSVD_3_W::new(self)
149    }
150    #[doc = "Bit 4"]
151    #[inline(always)]
152    #[must_use]
153    pub fn cr_urx_rto_clr(&mut self) -> CR_URX_RTO_CLR_W<4> {
154        CR_URX_RTO_CLR_W::new(self)
155    }
156    #[doc = "Bit 5"]
157    #[inline(always)]
158    #[must_use]
159    pub fn cr_urx_pce_clr(&mut self) -> CR_URX_PCE_CLR_W<5> {
160        CR_URX_PCE_CLR_W::new(self)
161    }
162    #[doc = "Bit 6"]
163    #[inline(always)]
164    #[must_use]
165    pub fn rsvd_6(&mut self) -> RSVD_6_W<6> {
166        RSVD_6_W::new(self)
167    }
168    #[doc = "Bit 7"]
169    #[inline(always)]
170    #[must_use]
171    pub fn rsvd_7(&mut self) -> RSVD_7_W<7> {
172        RSVD_7_W::new(self)
173    }
174    #[doc = "Bit 8"]
175    #[inline(always)]
176    #[must_use]
177    pub fn cr_urx_lse_clr(&mut self) -> CR_URX_LSE_CLR_W<8> {
178        CR_URX_LSE_CLR_W::new(self)
179    }
180    #[doc = "Writes raw bits to the register."]
181    #[inline(always)]
182    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183        self.0.bits(bits);
184        self
185    }
186}
187#[doc = "UART interrupt clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_clear](index.html) module"]
188pub struct UART_INT_CLEAR_SPEC;
189impl crate::RegisterSpec for UART_INT_CLEAR_SPEC {
190    type Ux = u32;
191}
192#[doc = "`read()` method returns [uart_int_clear::R](R) reader structure"]
193impl crate::Readable for UART_INT_CLEAR_SPEC {
194    type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [uart_int_clear::W](W) writer structure"]
197impl crate::Writable for UART_INT_CLEAR_SPEC {
198    type Writer = W;
199    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
200    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
201}
202#[doc = "`reset()` method sets uart_int_clear to value 0"]
203impl crate::Resettable for UART_INT_CLEAR_SPEC {
204    const RESET_VALUE: Self::Ux = 0;
205}
bl702_pac/uart/uart_int_clear.rs

bl702_pac/uart/
uart_int_clear.rs
