bl702_pac/sf_ctrl/
sf_if_io_dly_0.rs1#[doc = "Register `sf_if_io_dly_0` reader"]
2pub struct R(crate::R<SF_IF_IO_DLY_0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SF_IF_IO_DLY_0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SF_IF_IO_DLY_0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SF_IF_IO_DLY_0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `sf_if_io_dly_0` writer"]
17pub struct W(crate::W<SF_IF_IO_DLY_0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SF_IF_IO_DLY_0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SF_IF_IO_DLY_0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SF_IF_IO_DLY_0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `sf_cs_dly_sel` reader - "]
38pub type SF_CS_DLY_SEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `sf_cs_dly_sel` writer - "]
40pub type SF_CS_DLY_SEL_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, SF_IF_IO_DLY_0_SPEC, u8, u8, 2, O>;
42#[doc = "Field `sf_cs2_dly_sel` reader - "]
43pub type SF_CS2_DLY_SEL_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `sf_cs2_dly_sel` writer - "]
45pub type SF_CS2_DLY_SEL_W<'a, const O: u8> =
46 crate::FieldWriter<'a, u32, SF_IF_IO_DLY_0_SPEC, u8, u8, 2, O>;
47#[doc = "Field `sf_clk_out_dly_sel` reader - "]
48pub type SF_CLK_OUT_DLY_SEL_R = crate::FieldReader<u8, u8>;
49#[doc = "Field `sf_clk_out_dly_sel` writer - "]
50pub type SF_CLK_OUT_DLY_SEL_W<'a, const O: u8> =
51 crate::FieldWriter<'a, u32, SF_IF_IO_DLY_0_SPEC, u8, u8, 2, O>;
52#[doc = "Field `sf_dqs_oe_dly_sel` reader - "]
53pub type SF_DQS_OE_DLY_SEL_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `sf_dqs_oe_dly_sel` writer - "]
55pub type SF_DQS_OE_DLY_SEL_W<'a, const O: u8> =
56 crate::FieldWriter<'a, u32, SF_IF_IO_DLY_0_SPEC, u8, u8, 2, O>;
57#[doc = "Field `sf_dqs_di_dly_sel` reader - "]
58pub type SF_DQS_DI_DLY_SEL_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `sf_dqs_di_dly_sel` writer - "]
60pub type SF_DQS_DI_DLY_SEL_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, SF_IF_IO_DLY_0_SPEC, u8, u8, 2, O>;
62#[doc = "Field `sf_dqs_do_dly_sel` reader - "]
63pub type SF_DQS_DO_DLY_SEL_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `sf_dqs_do_dly_sel` writer - "]
65pub type SF_DQS_DO_DLY_SEL_W<'a, const O: u8> =
66 crate::FieldWriter<'a, u32, SF_IF_IO_DLY_0_SPEC, u8, u8, 2, O>;
67impl R {
68 #[doc = "Bits 0:1"]
69 #[inline(always)]
70 pub fn sf_cs_dly_sel(&self) -> SF_CS_DLY_SEL_R {
71 SF_CS_DLY_SEL_R::new((self.bits & 3) as u8)
72 }
73 #[doc = "Bits 2:3"]
74 #[inline(always)]
75 pub fn sf_cs2_dly_sel(&self) -> SF_CS2_DLY_SEL_R {
76 SF_CS2_DLY_SEL_R::new(((self.bits >> 2) & 3) as u8)
77 }
78 #[doc = "Bits 8:9"]
79 #[inline(always)]
80 pub fn sf_clk_out_dly_sel(&self) -> SF_CLK_OUT_DLY_SEL_R {
81 SF_CLK_OUT_DLY_SEL_R::new(((self.bits >> 8) & 3) as u8)
82 }
83 #[doc = "Bits 26:27"]
84 #[inline(always)]
85 pub fn sf_dqs_oe_dly_sel(&self) -> SF_DQS_OE_DLY_SEL_R {
86 SF_DQS_OE_DLY_SEL_R::new(((self.bits >> 26) & 3) as u8)
87 }
88 #[doc = "Bits 28:29"]
89 #[inline(always)]
90 pub fn sf_dqs_di_dly_sel(&self) -> SF_DQS_DI_DLY_SEL_R {
91 SF_DQS_DI_DLY_SEL_R::new(((self.bits >> 28) & 3) as u8)
92 }
93 #[doc = "Bits 30:31"]
94 #[inline(always)]
95 pub fn sf_dqs_do_dly_sel(&self) -> SF_DQS_DO_DLY_SEL_R {
96 SF_DQS_DO_DLY_SEL_R::new(((self.bits >> 30) & 3) as u8)
97 }
98}
99impl W {
100 #[doc = "Bits 0:1"]
101 #[inline(always)]
102 #[must_use]
103 pub fn sf_cs_dly_sel(&mut self) -> SF_CS_DLY_SEL_W<0> {
104 SF_CS_DLY_SEL_W::new(self)
105 }
106 #[doc = "Bits 2:3"]
107 #[inline(always)]
108 #[must_use]
109 pub fn sf_cs2_dly_sel(&mut self) -> SF_CS2_DLY_SEL_W<2> {
110 SF_CS2_DLY_SEL_W::new(self)
111 }
112 #[doc = "Bits 8:9"]
113 #[inline(always)]
114 #[must_use]
115 pub fn sf_clk_out_dly_sel(&mut self) -> SF_CLK_OUT_DLY_SEL_W<8> {
116 SF_CLK_OUT_DLY_SEL_W::new(self)
117 }
118 #[doc = "Bits 26:27"]
119 #[inline(always)]
120 #[must_use]
121 pub fn sf_dqs_oe_dly_sel(&mut self) -> SF_DQS_OE_DLY_SEL_W<26> {
122 SF_DQS_OE_DLY_SEL_W::new(self)
123 }
124 #[doc = "Bits 28:29"]
125 #[inline(always)]
126 #[must_use]
127 pub fn sf_dqs_di_dly_sel(&mut self) -> SF_DQS_DI_DLY_SEL_W<28> {
128 SF_DQS_DI_DLY_SEL_W::new(self)
129 }
130 #[doc = "Bits 30:31"]
131 #[inline(always)]
132 #[must_use]
133 pub fn sf_dqs_do_dly_sel(&mut self) -> SF_DQS_DO_DLY_SEL_W<30> {
134 SF_DQS_DO_DLY_SEL_W::new(self)
135 }
136 #[doc = "Writes raw bits to the register."]
137 #[inline(always)]
138 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
139 self.0.bits(bits);
140 self
141 }
142}
143#[doc = "sf_if_io_dly_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sf_if_io_dly_0](index.html) module"]
144pub struct SF_IF_IO_DLY_0_SPEC;
145impl crate::RegisterSpec for SF_IF_IO_DLY_0_SPEC {
146 type Ux = u32;
147}
148#[doc = "`read()` method returns [sf_if_io_dly_0::R](R) reader structure"]
149impl crate::Readable for SF_IF_IO_DLY_0_SPEC {
150 type Reader = R;
151}
152#[doc = "`write(|w| ..)` method takes [sf_if_io_dly_0::W](W) writer structure"]
153impl crate::Writable for SF_IF_IO_DLY_0_SPEC {
154 type Writer = W;
155 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
156 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
157}
158#[doc = "`reset()` method sets sf_if_io_dly_0 to value 0"]
159impl crate::Resettable for SF_IF_IO_DLY_0_SPEC {
160 const RESET_VALUE: Self::Ux = 0;
161}