bl702_pac/sec_eng/
se_sha_0_ctrl.rs

1#[doc = "Register `se_sha_0_ctrl` reader"]
2pub struct R(crate::R<SE_SHA_0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SE_SHA_0_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SE_SHA_0_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SE_SHA_0_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `se_sha_0_ctrl` writer"]
17pub struct W(crate::W<SE_SHA_0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SE_SHA_0_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SE_SHA_0_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SE_SHA_0_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `se_sha_0_busy` reader - "]
38pub type SE_SHA_0_BUSY_R = crate::BitReader<bool>;
39#[doc = "Field `se_sha_0_busy` writer - "]
40pub type SE_SHA_0_BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
41#[doc = "Field `se_sha_0_trig_1t` reader - "]
42pub type SE_SHA_0_TRIG_1T_R = crate::BitReader<bool>;
43#[doc = "Field `se_sha_0_trig_1t` writer - "]
44pub type SE_SHA_0_TRIG_1T_W<'a, const O: u8> =
45    crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
46#[doc = "Field `se_sha_0_mode` reader - "]
47pub type SE_SHA_0_MODE_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `se_sha_0_mode` writer - "]
49pub type SE_SHA_0_MODE_W<'a, const O: u8> =
50    crate::FieldWriter<'a, u32, SE_SHA_0_CTRL_SPEC, u8, u8, 3, O>;
51#[doc = "Field `se_sha_0_en` reader - "]
52pub type SE_SHA_0_EN_R = crate::BitReader<bool>;
53#[doc = "Field `se_sha_0_en` writer - "]
54pub type SE_SHA_0_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
55#[doc = "Field `se_sha_0_hash_sel` reader - "]
56pub type SE_SHA_0_HASH_SEL_R = crate::BitReader<bool>;
57#[doc = "Field `se_sha_0_hash_sel` writer - "]
58pub type SE_SHA_0_HASH_SEL_W<'a, const O: u8> =
59    crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
60#[doc = "Field `se_sha_0_int` reader - "]
61pub type SE_SHA_0_INT_R = crate::BitReader<bool>;
62#[doc = "Field `se_sha_0_int` writer - "]
63pub type SE_SHA_0_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
64#[doc = "Field `se_sha_0_int_clr_1t` reader - "]
65pub type SE_SHA_0_INT_CLR_1T_R = crate::BitReader<bool>;
66#[doc = "Field `se_sha_0_int_clr_1t` writer - "]
67pub type SE_SHA_0_INT_CLR_1T_W<'a, const O: u8> =
68    crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
69#[doc = "Field `se_sha_0_int_set_1t` reader - "]
70pub type SE_SHA_0_INT_SET_1T_R = crate::BitReader<bool>;
71#[doc = "Field `se_sha_0_int_set_1t` writer - "]
72pub type SE_SHA_0_INT_SET_1T_W<'a, const O: u8> =
73    crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
74#[doc = "Field `se_sha_0_int_mask` reader - "]
75pub type SE_SHA_0_INT_MASK_R = crate::BitReader<bool>;
76#[doc = "Field `se_sha_0_int_mask` writer - "]
77pub type SE_SHA_0_INT_MASK_W<'a, const O: u8> =
78    crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
79#[doc = "Field `se_sha_0_link_mode` reader - "]
80pub type SE_SHA_0_LINK_MODE_R = crate::BitReader<bool>;
81#[doc = "Field `se_sha_0_link_mode` writer - "]
82pub type SE_SHA_0_LINK_MODE_W<'a, const O: u8> =
83    crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
84#[doc = "Field `se_sha_0_msg_len` reader - "]
85pub type SE_SHA_0_MSG_LEN_R = crate::FieldReader<u16, u16>;
86#[doc = "Field `se_sha_0_msg_len` writer - "]
87pub type SE_SHA_0_MSG_LEN_W<'a, const O: u8> =
88    crate::FieldWriter<'a, u32, SE_SHA_0_CTRL_SPEC, u16, u16, 16, O>;
89impl R {
90    #[doc = "Bit 0"]
91    #[inline(always)]
92    pub fn se_sha_0_busy(&self) -> SE_SHA_0_BUSY_R {
93        SE_SHA_0_BUSY_R::new((self.bits & 1) != 0)
94    }
95    #[doc = "Bit 1"]
96    #[inline(always)]
97    pub fn se_sha_0_trig_1t(&self) -> SE_SHA_0_TRIG_1T_R {
98        SE_SHA_0_TRIG_1T_R::new(((self.bits >> 1) & 1) != 0)
99    }
100    #[doc = "Bits 2:4"]
101    #[inline(always)]
102    pub fn se_sha_0_mode(&self) -> SE_SHA_0_MODE_R {
103        SE_SHA_0_MODE_R::new(((self.bits >> 2) & 7) as u8)
104    }
105    #[doc = "Bit 5"]
106    #[inline(always)]
107    pub fn se_sha_0_en(&self) -> SE_SHA_0_EN_R {
108        SE_SHA_0_EN_R::new(((self.bits >> 5) & 1) != 0)
109    }
110    #[doc = "Bit 6"]
111    #[inline(always)]
112    pub fn se_sha_0_hash_sel(&self) -> SE_SHA_0_HASH_SEL_R {
113        SE_SHA_0_HASH_SEL_R::new(((self.bits >> 6) & 1) != 0)
114    }
115    #[doc = "Bit 8"]
116    #[inline(always)]
117    pub fn se_sha_0_int(&self) -> SE_SHA_0_INT_R {
118        SE_SHA_0_INT_R::new(((self.bits >> 8) & 1) != 0)
119    }
120    #[doc = "Bit 9"]
121    #[inline(always)]
122    pub fn se_sha_0_int_clr_1t(&self) -> SE_SHA_0_INT_CLR_1T_R {
123        SE_SHA_0_INT_CLR_1T_R::new(((self.bits >> 9) & 1) != 0)
124    }
125    #[doc = "Bit 10"]
126    #[inline(always)]
127    pub fn se_sha_0_int_set_1t(&self) -> SE_SHA_0_INT_SET_1T_R {
128        SE_SHA_0_INT_SET_1T_R::new(((self.bits >> 10) & 1) != 0)
129    }
130    #[doc = "Bit 11"]
131    #[inline(always)]
132    pub fn se_sha_0_int_mask(&self) -> SE_SHA_0_INT_MASK_R {
133        SE_SHA_0_INT_MASK_R::new(((self.bits >> 11) & 1) != 0)
134    }
135    #[doc = "Bit 15"]
136    #[inline(always)]
137    pub fn se_sha_0_link_mode(&self) -> SE_SHA_0_LINK_MODE_R {
138        SE_SHA_0_LINK_MODE_R::new(((self.bits >> 15) & 1) != 0)
139    }
140    #[doc = "Bits 16:31"]
141    #[inline(always)]
142    pub fn se_sha_0_msg_len(&self) -> SE_SHA_0_MSG_LEN_R {
143        SE_SHA_0_MSG_LEN_R::new(((self.bits >> 16) & 0xffff) as u16)
144    }
145}
146impl W {
147    #[doc = "Bit 0"]
148    #[inline(always)]
149    #[must_use]
150    pub fn se_sha_0_busy(&mut self) -> SE_SHA_0_BUSY_W<0> {
151        SE_SHA_0_BUSY_W::new(self)
152    }
153    #[doc = "Bit 1"]
154    #[inline(always)]
155    #[must_use]
156    pub fn se_sha_0_trig_1t(&mut self) -> SE_SHA_0_TRIG_1T_W<1> {
157        SE_SHA_0_TRIG_1T_W::new(self)
158    }
159    #[doc = "Bits 2:4"]
160    #[inline(always)]
161    #[must_use]
162    pub fn se_sha_0_mode(&mut self) -> SE_SHA_0_MODE_W<2> {
163        SE_SHA_0_MODE_W::new(self)
164    }
165    #[doc = "Bit 5"]
166    #[inline(always)]
167    #[must_use]
168    pub fn se_sha_0_en(&mut self) -> SE_SHA_0_EN_W<5> {
169        SE_SHA_0_EN_W::new(self)
170    }
171    #[doc = "Bit 6"]
172    #[inline(always)]
173    #[must_use]
174    pub fn se_sha_0_hash_sel(&mut self) -> SE_SHA_0_HASH_SEL_W<6> {
175        SE_SHA_0_HASH_SEL_W::new(self)
176    }
177    #[doc = "Bit 8"]
178    #[inline(always)]
179    #[must_use]
180    pub fn se_sha_0_int(&mut self) -> SE_SHA_0_INT_W<8> {
181        SE_SHA_0_INT_W::new(self)
182    }
183    #[doc = "Bit 9"]
184    #[inline(always)]
185    #[must_use]
186    pub fn se_sha_0_int_clr_1t(&mut self) -> SE_SHA_0_INT_CLR_1T_W<9> {
187        SE_SHA_0_INT_CLR_1T_W::new(self)
188    }
189    #[doc = "Bit 10"]
190    #[inline(always)]
191    #[must_use]
192    pub fn se_sha_0_int_set_1t(&mut self) -> SE_SHA_0_INT_SET_1T_W<10> {
193        SE_SHA_0_INT_SET_1T_W::new(self)
194    }
195    #[doc = "Bit 11"]
196    #[inline(always)]
197    #[must_use]
198    pub fn se_sha_0_int_mask(&mut self) -> SE_SHA_0_INT_MASK_W<11> {
199        SE_SHA_0_INT_MASK_W::new(self)
200    }
201    #[doc = "Bit 15"]
202    #[inline(always)]
203    #[must_use]
204    pub fn se_sha_0_link_mode(&mut self) -> SE_SHA_0_LINK_MODE_W<15> {
205        SE_SHA_0_LINK_MODE_W::new(self)
206    }
207    #[doc = "Bits 16:31"]
208    #[inline(always)]
209    #[must_use]
210    pub fn se_sha_0_msg_len(&mut self) -> SE_SHA_0_MSG_LEN_W<16> {
211        SE_SHA_0_MSG_LEN_W::new(self)
212    }
213    #[doc = "Writes raw bits to the register."]
214    #[inline(always)]
215    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
216        self.0.bits(bits);
217        self
218    }
219}
220#[doc = "se_sha_0_ctrl.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [se_sha_0_ctrl](index.html) module"]
221pub struct SE_SHA_0_CTRL_SPEC;
222impl crate::RegisterSpec for SE_SHA_0_CTRL_SPEC {
223    type Ux = u32;
224}
225#[doc = "`read()` method returns [se_sha_0_ctrl::R](R) reader structure"]
226impl crate::Readable for SE_SHA_0_CTRL_SPEC {
227    type Reader = R;
228}
229#[doc = "`write(|w| ..)` method takes [se_sha_0_ctrl::W](W) writer structure"]
230impl crate::Writable for SE_SHA_0_CTRL_SPEC {
231    type Writer = W;
232    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
233    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
234}
235#[doc = "`reset()` method sets se_sha_0_ctrl to value 0"]
236impl crate::Resettable for SE_SHA_0_CTRL_SPEC {
237    const RESET_VALUE: Self::Ux = 0;
238}
bl702_pac/sec_eng/se_sha_0_ctrl.rs

bl702_pac/sec_eng/
se_sha_0_ctrl.rs
