bl702_pac/sec_eng/
se_pka_0_ctrl_0.rs1#[doc = "Register `se_pka_0_ctrl_0` reader"]
2pub struct R(crate::R<SE_PKA_0_CTRL_0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SE_PKA_0_CTRL_0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SE_PKA_0_CTRL_0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SE_PKA_0_CTRL_0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `se_pka_0_ctrl_0` writer"]
17pub struct W(crate::W<SE_PKA_0_CTRL_0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SE_PKA_0_CTRL_0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SE_PKA_0_CTRL_0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SE_PKA_0_CTRL_0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `se_pka_0_done` reader - "]
38pub type SE_PKA_0_DONE_R = crate::BitReader<bool>;
39#[doc = "Field `se_pka_0_done` writer - "]
40pub type SE_PKA_0_DONE_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
42#[doc = "Field `se_pka_0_done_clr_1t` reader - "]
43pub type SE_PKA_0_DONE_CLR_1T_R = crate::BitReader<bool>;
44#[doc = "Field `se_pka_0_done_clr_1t` writer - "]
45pub type SE_PKA_0_DONE_CLR_1T_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
47#[doc = "Field `se_pka_0_busy` reader - "]
48pub type SE_PKA_0_BUSY_R = crate::BitReader<bool>;
49#[doc = "Field `se_pka_0_busy` writer - "]
50pub type SE_PKA_0_BUSY_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
52#[doc = "Field `se_pka_0_en` reader - "]
53pub type SE_PKA_0_EN_R = crate::BitReader<bool>;
54#[doc = "Field `se_pka_0_en` writer - "]
55pub type SE_PKA_0_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
56#[doc = "Field `se_pka_0_prot_md` reader - "]
57pub type SE_PKA_0_PROT_MD_R = crate::FieldReader<u8, u8>;
58#[doc = "Field `se_pka_0_prot_md` writer - "]
59pub type SE_PKA_0_PROT_MD_W<'a, const O: u8> =
60 crate::FieldWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, u8, u8, 4, O>;
61#[doc = "Field `se_pka_0_int` reader - "]
62pub type SE_PKA_0_INT_R = crate::BitReader<bool>;
63#[doc = "Field `se_pka_0_int` writer - "]
64pub type SE_PKA_0_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
65#[doc = "Field `se_pka_0_int_clr_1t` reader - "]
66pub type SE_PKA_0_INT_CLR_1T_R = crate::BitReader<bool>;
67#[doc = "Field `se_pka_0_int_clr_1t` writer - "]
68pub type SE_PKA_0_INT_CLR_1T_W<'a, const O: u8> =
69 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
70#[doc = "Field `se_pka_0_int_set` reader - "]
71pub type SE_PKA_0_INT_SET_R = crate::BitReader<bool>;
72#[doc = "Field `se_pka_0_int_set` writer - "]
73pub type SE_PKA_0_INT_SET_W<'a, const O: u8> =
74 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
75#[doc = "Field `se_pka_0_int_mask` reader - "]
76pub type SE_PKA_0_INT_MASK_R = crate::BitReader<bool>;
77#[doc = "Field `se_pka_0_int_mask` writer - "]
78pub type SE_PKA_0_INT_MASK_W<'a, const O: u8> =
79 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
80#[doc = "Field `se_pka_0_endian` reader - "]
81pub type SE_PKA_0_ENDIAN_R = crate::BitReader<bool>;
82#[doc = "Field `se_pka_0_endian` writer - "]
83pub type SE_PKA_0_ENDIAN_W<'a, const O: u8> =
84 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
85#[doc = "Field `se_pka_0_ram_clr_md` reader - "]
86pub type SE_PKA_0_RAM_CLR_MD_R = crate::BitReader<bool>;
87#[doc = "Field `se_pka_0_ram_clr_md` writer - "]
88pub type SE_PKA_0_RAM_CLR_MD_W<'a, const O: u8> =
89 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
90#[doc = "Field `se_pka_0_status_clr_1t` reader - "]
91pub type SE_PKA_0_STATUS_CLR_1T_R = crate::BitReader<bool>;
92#[doc = "Field `se_pka_0_status_clr_1t` writer - "]
93pub type SE_PKA_0_STATUS_CLR_1T_W<'a, const O: u8> =
94 crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
95#[doc = "Field `se_pka_0_status` reader - "]
96pub type SE_PKA_0_STATUS_R = crate::FieldReader<u16, u16>;
97#[doc = "Field `se_pka_0_status` writer - "]
98pub type SE_PKA_0_STATUS_W<'a, const O: u8> =
99 crate::FieldWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, u16, u16, 16, O>;
100impl R {
101 #[doc = "Bit 0"]
102 #[inline(always)]
103 pub fn se_pka_0_done(&self) -> SE_PKA_0_DONE_R {
104 SE_PKA_0_DONE_R::new((self.bits & 1) != 0)
105 }
106 #[doc = "Bit 1"]
107 #[inline(always)]
108 pub fn se_pka_0_done_clr_1t(&self) -> SE_PKA_0_DONE_CLR_1T_R {
109 SE_PKA_0_DONE_CLR_1T_R::new(((self.bits >> 1) & 1) != 0)
110 }
111 #[doc = "Bit 2"]
112 #[inline(always)]
113 pub fn se_pka_0_busy(&self) -> SE_PKA_0_BUSY_R {
114 SE_PKA_0_BUSY_R::new(((self.bits >> 2) & 1) != 0)
115 }
116 #[doc = "Bit 3"]
117 #[inline(always)]
118 pub fn se_pka_0_en(&self) -> SE_PKA_0_EN_R {
119 SE_PKA_0_EN_R::new(((self.bits >> 3) & 1) != 0)
120 }
121 #[doc = "Bits 4:7"]
122 #[inline(always)]
123 pub fn se_pka_0_prot_md(&self) -> SE_PKA_0_PROT_MD_R {
124 SE_PKA_0_PROT_MD_R::new(((self.bits >> 4) & 0x0f) as u8)
125 }
126 #[doc = "Bit 8"]
127 #[inline(always)]
128 pub fn se_pka_0_int(&self) -> SE_PKA_0_INT_R {
129 SE_PKA_0_INT_R::new(((self.bits >> 8) & 1) != 0)
130 }
131 #[doc = "Bit 9"]
132 #[inline(always)]
133 pub fn se_pka_0_int_clr_1t(&self) -> SE_PKA_0_INT_CLR_1T_R {
134 SE_PKA_0_INT_CLR_1T_R::new(((self.bits >> 9) & 1) != 0)
135 }
136 #[doc = "Bit 10"]
137 #[inline(always)]
138 pub fn se_pka_0_int_set(&self) -> SE_PKA_0_INT_SET_R {
139 SE_PKA_0_INT_SET_R::new(((self.bits >> 10) & 1) != 0)
140 }
141 #[doc = "Bit 11"]
142 #[inline(always)]
143 pub fn se_pka_0_int_mask(&self) -> SE_PKA_0_INT_MASK_R {
144 SE_PKA_0_INT_MASK_R::new(((self.bits >> 11) & 1) != 0)
145 }
146 #[doc = "Bit 12"]
147 #[inline(always)]
148 pub fn se_pka_0_endian(&self) -> SE_PKA_0_ENDIAN_R {
149 SE_PKA_0_ENDIAN_R::new(((self.bits >> 12) & 1) != 0)
150 }
151 #[doc = "Bit 13"]
152 #[inline(always)]
153 pub fn se_pka_0_ram_clr_md(&self) -> SE_PKA_0_RAM_CLR_MD_R {
154 SE_PKA_0_RAM_CLR_MD_R::new(((self.bits >> 13) & 1) != 0)
155 }
156 #[doc = "Bit 15"]
157 #[inline(always)]
158 pub fn se_pka_0_status_clr_1t(&self) -> SE_PKA_0_STATUS_CLR_1T_R {
159 SE_PKA_0_STATUS_CLR_1T_R::new(((self.bits >> 15) & 1) != 0)
160 }
161 #[doc = "Bits 16:31"]
162 #[inline(always)]
163 pub fn se_pka_0_status(&self) -> SE_PKA_0_STATUS_R {
164 SE_PKA_0_STATUS_R::new(((self.bits >> 16) & 0xffff) as u16)
165 }
166}
167impl W {
168 #[doc = "Bit 0"]
169 #[inline(always)]
170 #[must_use]
171 pub fn se_pka_0_done(&mut self) -> SE_PKA_0_DONE_W<0> {
172 SE_PKA_0_DONE_W::new(self)
173 }
174 #[doc = "Bit 1"]
175 #[inline(always)]
176 #[must_use]
177 pub fn se_pka_0_done_clr_1t(&mut self) -> SE_PKA_0_DONE_CLR_1T_W<1> {
178 SE_PKA_0_DONE_CLR_1T_W::new(self)
179 }
180 #[doc = "Bit 2"]
181 #[inline(always)]
182 #[must_use]
183 pub fn se_pka_0_busy(&mut self) -> SE_PKA_0_BUSY_W<2> {
184 SE_PKA_0_BUSY_W::new(self)
185 }
186 #[doc = "Bit 3"]
187 #[inline(always)]
188 #[must_use]
189 pub fn se_pka_0_en(&mut self) -> SE_PKA_0_EN_W<3> {
190 SE_PKA_0_EN_W::new(self)
191 }
192 #[doc = "Bits 4:7"]
193 #[inline(always)]
194 #[must_use]
195 pub fn se_pka_0_prot_md(&mut self) -> SE_PKA_0_PROT_MD_W<4> {
196 SE_PKA_0_PROT_MD_W::new(self)
197 }
198 #[doc = "Bit 8"]
199 #[inline(always)]
200 #[must_use]
201 pub fn se_pka_0_int(&mut self) -> SE_PKA_0_INT_W<8> {
202 SE_PKA_0_INT_W::new(self)
203 }
204 #[doc = "Bit 9"]
205 #[inline(always)]
206 #[must_use]
207 pub fn se_pka_0_int_clr_1t(&mut self) -> SE_PKA_0_INT_CLR_1T_W<9> {
208 SE_PKA_0_INT_CLR_1T_W::new(self)
209 }
210 #[doc = "Bit 10"]
211 #[inline(always)]
212 #[must_use]
213 pub fn se_pka_0_int_set(&mut self) -> SE_PKA_0_INT_SET_W<10> {
214 SE_PKA_0_INT_SET_W::new(self)
215 }
216 #[doc = "Bit 11"]
217 #[inline(always)]
218 #[must_use]
219 pub fn se_pka_0_int_mask(&mut self) -> SE_PKA_0_INT_MASK_W<11> {
220 SE_PKA_0_INT_MASK_W::new(self)
221 }
222 #[doc = "Bit 12"]
223 #[inline(always)]
224 #[must_use]
225 pub fn se_pka_0_endian(&mut self) -> SE_PKA_0_ENDIAN_W<12> {
226 SE_PKA_0_ENDIAN_W::new(self)
227 }
228 #[doc = "Bit 13"]
229 #[inline(always)]
230 #[must_use]
231 pub fn se_pka_0_ram_clr_md(&mut self) -> SE_PKA_0_RAM_CLR_MD_W<13> {
232 SE_PKA_0_RAM_CLR_MD_W::new(self)
233 }
234 #[doc = "Bit 15"]
235 #[inline(always)]
236 #[must_use]
237 pub fn se_pka_0_status_clr_1t(&mut self) -> SE_PKA_0_STATUS_CLR_1T_W<15> {
238 SE_PKA_0_STATUS_CLR_1T_W::new(self)
239 }
240 #[doc = "Bits 16:31"]
241 #[inline(always)]
242 #[must_use]
243 pub fn se_pka_0_status(&mut self) -> SE_PKA_0_STATUS_W<16> {
244 SE_PKA_0_STATUS_W::new(self)
245 }
246 #[doc = "Writes raw bits to the register."]
247 #[inline(always)]
248 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
249 self.0.bits(bits);
250 self
251 }
252}
253#[doc = "se_pka_0_ctrl_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [se_pka_0_ctrl_0](index.html) module"]
254pub struct SE_PKA_0_CTRL_0_SPEC;
255impl crate::RegisterSpec for SE_PKA_0_CTRL_0_SPEC {
256 type Ux = u32;
257}
258#[doc = "`read()` method returns [se_pka_0_ctrl_0::R](R) reader structure"]
259impl crate::Readable for SE_PKA_0_CTRL_0_SPEC {
260 type Reader = R;
261}
262#[doc = "`write(|w| ..)` method takes [se_pka_0_ctrl_0::W](W) writer structure"]
263impl crate::Writable for SE_PKA_0_CTRL_0_SPEC {
264 type Writer = W;
265 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
266 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
267}
268#[doc = "`reset()` method sets se_pka_0_ctrl_0 to value 0"]
269impl crate::Resettable for SE_PKA_0_CTRL_0_SPEC {
270 const RESET_VALUE: Self::Ux = 0;
271}