1#[doc = "Register `rxadc` reader"]
2pub struct R(crate::R<RXADC_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<RXADC_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<RXADC_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<RXADC_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `rxadc` writer"]
17pub struct W(crate::W<RXADC_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<RXADC_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<RXADC_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<RXADC_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `rxadc_oscal_en` reader - "]
38pub type RXADC_OSCAL_EN_R = crate::BitReader<bool>;
39#[doc = "Field `rxadc_oscal_en` writer - "]
40pub type RXADC_OSCAL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXADC_SPEC, bool, O>;
41#[doc = "Field `rxadc_vref_sel` reader - "]
42pub type RXADC_VREF_SEL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `rxadc_vref_sel` writer - "]
44pub type RXADC_VREF_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXADC_SPEC, u8, u8, 2, O>;
45#[doc = "Field `rxadc_clk_sync_inv` reader - "]
46pub type RXADC_CLK_SYNC_INV_R = crate::BitReader<bool>;
47#[doc = "Field `rxadc_clk_sync_inv` writer - "]
48pub type RXADC_CLK_SYNC_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXADC_SPEC, bool, O>;
49#[doc = "Field `rxadc_clk_inv` reader - "]
50pub type RXADC_CLK_INV_R = crate::BitReader<bool>;
51#[doc = "Field `rxadc_clk_inv` writer - "]
52pub type RXADC_CLK_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXADC_SPEC, bool, O>;
53#[doc = "Field `rxadc_clk_div_sel` reader - "]
54pub type RXADC_CLK_DIV_SEL_R = crate::BitReader<bool>;
55#[doc = "Field `rxadc_clk_div_sel` writer - "]
56pub type RXADC_CLK_DIV_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXADC_SPEC, bool, O>;
57#[doc = "Field `rxadc_glitch_remove` reader - "]
58pub type RXADC_GLITCH_REMOVE_R = crate::BitReader<bool>;
59#[doc = "Field `rxadc_glitch_remove` writer - "]
60pub type RXADC_GLITCH_REMOVE_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXADC_SPEC, bool, O>;
61#[doc = "Field `rxadc_dly_ctrl` reader - "]
62pub type RXADC_DLY_CTRL_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `rxadc_dly_ctrl` writer - "]
64pub type RXADC_DLY_CTRL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXADC_SPEC, u8, u8, 2, O>;
65impl R {
66 #[doc = "Bit 0"]
67 #[inline(always)]
68 pub fn rxadc_oscal_en(&self) -> RXADC_OSCAL_EN_R {
69 RXADC_OSCAL_EN_R::new((self.bits & 1) != 0)
70 }
71 #[doc = "Bits 4:5"]
72 #[inline(always)]
73 pub fn rxadc_vref_sel(&self) -> RXADC_VREF_SEL_R {
74 RXADC_VREF_SEL_R::new(((self.bits >> 4) & 3) as u8)
75 }
76 #[doc = "Bit 8"]
77 #[inline(always)]
78 pub fn rxadc_clk_sync_inv(&self) -> RXADC_CLK_SYNC_INV_R {
79 RXADC_CLK_SYNC_INV_R::new(((self.bits >> 8) & 1) != 0)
80 }
81 #[doc = "Bit 12"]
82 #[inline(always)]
83 pub fn rxadc_clk_inv(&self) -> RXADC_CLK_INV_R {
84 RXADC_CLK_INV_R::new(((self.bits >> 12) & 1) != 0)
85 }
86 #[doc = "Bit 16"]
87 #[inline(always)]
88 pub fn rxadc_clk_div_sel(&self) -> RXADC_CLK_DIV_SEL_R {
89 RXADC_CLK_DIV_SEL_R::new(((self.bits >> 16) & 1) != 0)
90 }
91 #[doc = "Bit 20"]
92 #[inline(always)]
93 pub fn rxadc_glitch_remove(&self) -> RXADC_GLITCH_REMOVE_R {
94 RXADC_GLITCH_REMOVE_R::new(((self.bits >> 20) & 1) != 0)
95 }
96 #[doc = "Bits 24:25"]
97 #[inline(always)]
98 pub fn rxadc_dly_ctrl(&self) -> RXADC_DLY_CTRL_R {
99 RXADC_DLY_CTRL_R::new(((self.bits >> 24) & 3) as u8)
100 }
101}
102impl W {
103 #[doc = "Bit 0"]
104 #[inline(always)]
105 #[must_use]
106 pub fn rxadc_oscal_en(&mut self) -> RXADC_OSCAL_EN_W<0> {
107 RXADC_OSCAL_EN_W::new(self)
108 }
109 #[doc = "Bits 4:5"]
110 #[inline(always)]
111 #[must_use]
112 pub fn rxadc_vref_sel(&mut self) -> RXADC_VREF_SEL_W<4> {
113 RXADC_VREF_SEL_W::new(self)
114 }
115 #[doc = "Bit 8"]
116 #[inline(always)]
117 #[must_use]
118 pub fn rxadc_clk_sync_inv(&mut self) -> RXADC_CLK_SYNC_INV_W<8> {
119 RXADC_CLK_SYNC_INV_W::new(self)
120 }
121 #[doc = "Bit 12"]
122 #[inline(always)]
123 #[must_use]
124 pub fn rxadc_clk_inv(&mut self) -> RXADC_CLK_INV_W<12> {
125 RXADC_CLK_INV_W::new(self)
126 }
127 #[doc = "Bit 16"]
128 #[inline(always)]
129 #[must_use]
130 pub fn rxadc_clk_div_sel(&mut self) -> RXADC_CLK_DIV_SEL_W<16> {
131 RXADC_CLK_DIV_SEL_W::new(self)
132 }
133 #[doc = "Bit 20"]
134 #[inline(always)]
135 #[must_use]
136 pub fn rxadc_glitch_remove(&mut self) -> RXADC_GLITCH_REMOVE_W<20> {
137 RXADC_GLITCH_REMOVE_W::new(self)
138 }
139 #[doc = "Bits 24:25"]
140 #[inline(always)]
141 #[must_use]
142 pub fn rxadc_dly_ctrl(&mut self) -> RXADC_DLY_CTRL_W<24> {
143 RXADC_DLY_CTRL_W::new(self)
144 }
145 #[doc = "Writes raw bits to the register."]
146 #[inline(always)]
147 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
148 self.0.bits(bits);
149 self
150 }
151}
152#[doc = "rxadc.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxadc](index.html) module"]
153pub struct RXADC_SPEC;
154impl crate::RegisterSpec for RXADC_SPEC {
155 type Ux = u32;
156}
157#[doc = "`read()` method returns [rxadc::R](R) reader structure"]
158impl crate::Readable for RXADC_SPEC {
159 type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [rxadc::W](W) writer structure"]
162impl crate::Writable for RXADC_SPEC {
163 type Writer = W;
164 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets rxadc to value 0"]
168impl crate::Resettable for RXADC_SPEC {
169 const RESET_VALUE: Self::Ux = 0;
170}