bl702_pac/rf/
adpll_vctrl.rs1#[doc = "Register `adpll_vctrl` reader"]
2pub struct R(crate::R<ADPLL_VCTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ADPLL_VCTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ADPLL_VCTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ADPLL_VCTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `adpll_vctrl` writer"]
17pub struct W(crate::W<ADPLL_VCTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ADPLL_VCTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ADPLL_VCTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ADPLL_VCTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `sdmout_dly_sel` reader - "]
38pub type SDMOUT_DLY_SEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `sdmout_dly_sel` writer - "]
40pub type SDMOUT_DLY_SEL_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, ADPLL_VCTRL_SPEC, u8, u8, 2, O>;
42#[doc = "Field `sdm_bypass` reader - "]
43pub type SDM_BYPASS_R = crate::BitReader<bool>;
44#[doc = "Field `sdm_bypass` writer - "]
45pub type SDM_BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
46#[doc = "Field `sdm_dither` reader - "]
47pub type SDM_DITHER_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `sdm_dither` writer - "]
49pub type SDM_DITHER_W<'a, const O: u8> =
50 crate::FieldWriter<'a, u32, ADPLL_VCTRL_SPEC, u8, u8, 2, O>;
51#[doc = "Field `sdm_order` reader - "]
52pub type SDM_ORDER_R = crate::BitReader<bool>;
53#[doc = "Field `sdm_order` writer - "]
54pub type SDM_ORDER_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
55#[doc = "Field `adpll_capcode_bypass` reader - "]
56pub type ADPLL_CAPCODE_BYPASS_R = crate::BitReader<bool>;
57#[doc = "Field `adpll_capcode_bypass` writer - "]
58pub type ADPLL_CAPCODE_BYPASS_W<'a, const O: u8> =
59 crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
60#[doc = "Field `adpll_dco_mash_bypass` reader - "]
61pub type ADPLL_DCO_MASH_BYPASS_R = crate::BitReader<bool>;
62#[doc = "Field `adpll_dco_mash_bypass` writer - "]
63pub type ADPLL_DCO_MASH_BYPASS_W<'a, const O: u8> =
64 crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
65#[doc = "Field `adpll_force_mom_hold` reader - "]
66pub type ADPLL_FORCE_MOM_HOLD_R = crate::BitReader<bool>;
67#[doc = "Field `adpll_force_mom_hold` writer - "]
68pub type ADPLL_FORCE_MOM_HOLD_W<'a, const O: u8> =
69 crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
70#[doc = "Field `adpll_mom_update_period` reader - "]
71pub type ADPLL_MOM_UPDATE_PERIOD_R = crate::FieldReader<u8, u8>;
72#[doc = "Field `adpll_mom_update_period` writer - "]
73pub type ADPLL_MOM_UPDATE_PERIOD_W<'a, const O: u8> =
74 crate::FieldWriter<'a, u32, ADPLL_VCTRL_SPEC, u8, u8, 2, O>;
75#[doc = "Field `adpll_vctrl_det_cons_en` reader - "]
76pub type ADPLL_VCTRL_DET_CONS_EN_R = crate::BitReader<bool>;
77#[doc = "Field `adpll_vctrl_det_cons_en` writer - "]
78pub type ADPLL_VCTRL_DET_CONS_EN_W<'a, const O: u8> =
79 crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
80#[doc = "Field `adpll_vctrl_moni_win_sel` reader - "]
81pub type ADPLL_VCTRL_MONI_WIN_SEL_R = crate::BitReader<bool>;
82#[doc = "Field `adpll_vctrl_moni_win_sel` writer - "]
83pub type ADPLL_VCTRL_MONI_WIN_SEL_W<'a, const O: u8> =
84 crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
85#[doc = "Field `adpll_vctrl_lock_win_sel` reader - "]
86pub type ADPLL_VCTRL_LOCK_WIN_SEL_R = crate::BitReader<bool>;
87#[doc = "Field `adpll_vctrl_lock_win_sel` writer - "]
88pub type ADPLL_VCTRL_LOCK_WIN_SEL_W<'a, const O: u8> =
89 crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
90#[doc = "Field `adpll_vctrl_range_sel_ext_en` reader - "]
91pub type ADPLL_VCTRL_RANGE_SEL_EXT_EN_R = crate::BitReader<bool>;
92#[doc = "Field `adpll_vctrl_range_sel_ext_en` writer - "]
93pub type ADPLL_VCTRL_RANGE_SEL_EXT_EN_W<'a, const O: u8> =
94 crate::BitWriter<'a, u32, ADPLL_VCTRL_SPEC, bool, O>;
95impl R {
96 #[doc = "Bits 0:1"]
97 #[inline(always)]
98 pub fn sdmout_dly_sel(&self) -> SDMOUT_DLY_SEL_R {
99 SDMOUT_DLY_SEL_R::new((self.bits & 3) as u8)
100 }
101 #[doc = "Bit 4"]
102 #[inline(always)]
103 pub fn sdm_bypass(&self) -> SDM_BYPASS_R {
104 SDM_BYPASS_R::new(((self.bits >> 4) & 1) != 0)
105 }
106 #[doc = "Bits 8:9"]
107 #[inline(always)]
108 pub fn sdm_dither(&self) -> SDM_DITHER_R {
109 SDM_DITHER_R::new(((self.bits >> 8) & 3) as u8)
110 }
111 #[doc = "Bit 12"]
112 #[inline(always)]
113 pub fn sdm_order(&self) -> SDM_ORDER_R {
114 SDM_ORDER_R::new(((self.bits >> 12) & 1) != 0)
115 }
116 #[doc = "Bit 14"]
117 #[inline(always)]
118 pub fn adpll_capcode_bypass(&self) -> ADPLL_CAPCODE_BYPASS_R {
119 ADPLL_CAPCODE_BYPASS_R::new(((self.bits >> 14) & 1) != 0)
120 }
121 #[doc = "Bit 15"]
122 #[inline(always)]
123 pub fn adpll_dco_mash_bypass(&self) -> ADPLL_DCO_MASH_BYPASS_R {
124 ADPLL_DCO_MASH_BYPASS_R::new(((self.bits >> 15) & 1) != 0)
125 }
126 #[doc = "Bit 16"]
127 #[inline(always)]
128 pub fn adpll_force_mom_hold(&self) -> ADPLL_FORCE_MOM_HOLD_R {
129 ADPLL_FORCE_MOM_HOLD_R::new(((self.bits >> 16) & 1) != 0)
130 }
131 #[doc = "Bits 20:21"]
132 #[inline(always)]
133 pub fn adpll_mom_update_period(&self) -> ADPLL_MOM_UPDATE_PERIOD_R {
134 ADPLL_MOM_UPDATE_PERIOD_R::new(((self.bits >> 20) & 3) as u8)
135 }
136 #[doc = "Bit 24"]
137 #[inline(always)]
138 pub fn adpll_vctrl_det_cons_en(&self) -> ADPLL_VCTRL_DET_CONS_EN_R {
139 ADPLL_VCTRL_DET_CONS_EN_R::new(((self.bits >> 24) & 1) != 0)
140 }
141 #[doc = "Bit 25"]
142 #[inline(always)]
143 pub fn adpll_vctrl_moni_win_sel(&self) -> ADPLL_VCTRL_MONI_WIN_SEL_R {
144 ADPLL_VCTRL_MONI_WIN_SEL_R::new(((self.bits >> 25) & 1) != 0)
145 }
146 #[doc = "Bit 26"]
147 #[inline(always)]
148 pub fn adpll_vctrl_lock_win_sel(&self) -> ADPLL_VCTRL_LOCK_WIN_SEL_R {
149 ADPLL_VCTRL_LOCK_WIN_SEL_R::new(((self.bits >> 26) & 1) != 0)
150 }
151 #[doc = "Bit 27"]
152 #[inline(always)]
153 pub fn adpll_vctrl_range_sel_ext_en(&self) -> ADPLL_VCTRL_RANGE_SEL_EXT_EN_R {
154 ADPLL_VCTRL_RANGE_SEL_EXT_EN_R::new(((self.bits >> 27) & 1) != 0)
155 }
156}
157impl W {
158 #[doc = "Bits 0:1"]
159 #[inline(always)]
160 #[must_use]
161 pub fn sdmout_dly_sel(&mut self) -> SDMOUT_DLY_SEL_W<0> {
162 SDMOUT_DLY_SEL_W::new(self)
163 }
164 #[doc = "Bit 4"]
165 #[inline(always)]
166 #[must_use]
167 pub fn sdm_bypass(&mut self) -> SDM_BYPASS_W<4> {
168 SDM_BYPASS_W::new(self)
169 }
170 #[doc = "Bits 8:9"]
171 #[inline(always)]
172 #[must_use]
173 pub fn sdm_dither(&mut self) -> SDM_DITHER_W<8> {
174 SDM_DITHER_W::new(self)
175 }
176 #[doc = "Bit 12"]
177 #[inline(always)]
178 #[must_use]
179 pub fn sdm_order(&mut self) -> SDM_ORDER_W<12> {
180 SDM_ORDER_W::new(self)
181 }
182 #[doc = "Bit 14"]
183 #[inline(always)]
184 #[must_use]
185 pub fn adpll_capcode_bypass(&mut self) -> ADPLL_CAPCODE_BYPASS_W<14> {
186 ADPLL_CAPCODE_BYPASS_W::new(self)
187 }
188 #[doc = "Bit 15"]
189 #[inline(always)]
190 #[must_use]
191 pub fn adpll_dco_mash_bypass(&mut self) -> ADPLL_DCO_MASH_BYPASS_W<15> {
192 ADPLL_DCO_MASH_BYPASS_W::new(self)
193 }
194 #[doc = "Bit 16"]
195 #[inline(always)]
196 #[must_use]
197 pub fn adpll_force_mom_hold(&mut self) -> ADPLL_FORCE_MOM_HOLD_W<16> {
198 ADPLL_FORCE_MOM_HOLD_W::new(self)
199 }
200 #[doc = "Bits 20:21"]
201 #[inline(always)]
202 #[must_use]
203 pub fn adpll_mom_update_period(&mut self) -> ADPLL_MOM_UPDATE_PERIOD_W<20> {
204 ADPLL_MOM_UPDATE_PERIOD_W::new(self)
205 }
206 #[doc = "Bit 24"]
207 #[inline(always)]
208 #[must_use]
209 pub fn adpll_vctrl_det_cons_en(&mut self) -> ADPLL_VCTRL_DET_CONS_EN_W<24> {
210 ADPLL_VCTRL_DET_CONS_EN_W::new(self)
211 }
212 #[doc = "Bit 25"]
213 #[inline(always)]
214 #[must_use]
215 pub fn adpll_vctrl_moni_win_sel(&mut self) -> ADPLL_VCTRL_MONI_WIN_SEL_W<25> {
216 ADPLL_VCTRL_MONI_WIN_SEL_W::new(self)
217 }
218 #[doc = "Bit 26"]
219 #[inline(always)]
220 #[must_use]
221 pub fn adpll_vctrl_lock_win_sel(&mut self) -> ADPLL_VCTRL_LOCK_WIN_SEL_W<26> {
222 ADPLL_VCTRL_LOCK_WIN_SEL_W::new(self)
223 }
224 #[doc = "Bit 27"]
225 #[inline(always)]
226 #[must_use]
227 pub fn adpll_vctrl_range_sel_ext_en(&mut self) -> ADPLL_VCTRL_RANGE_SEL_EXT_EN_W<27> {
228 ADPLL_VCTRL_RANGE_SEL_EXT_EN_W::new(self)
229 }
230 #[doc = "Writes raw bits to the register."]
231 #[inline(always)]
232 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
233 self.0.bits(bits);
234 self
235 }
236}
237#[doc = "adpll_vctrl.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adpll_vctrl](index.html) module"]
238pub struct ADPLL_VCTRL_SPEC;
239impl crate::RegisterSpec for ADPLL_VCTRL_SPEC {
240 type Ux = u32;
241}
242#[doc = "`read()` method returns [adpll_vctrl::R](R) reader structure"]
243impl crate::Readable for ADPLL_VCTRL_SPEC {
244 type Reader = R;
245}
246#[doc = "`write(|w| ..)` method takes [adpll_vctrl::W](W) writer structure"]
247impl crate::Writable for ADPLL_VCTRL_SPEC {
248 type Writer = W;
249 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
250 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
251}
252#[doc = "`reset()` method sets adpll_vctrl to value 0"]
253impl crate::Resettable for ADPLL_VCTRL_SPEC {
254 const RESET_VALUE: Self::Ux = 0;
255}