1#[doc = "Register `adpll_spd` reader"]
2pub struct R(crate::R<ADPLL_SPD_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ADPLL_SPD_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ADPLL_SPD_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ADPLL_SPD_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `adpll_spd` writer"]
17pub struct W(crate::W<ADPLL_SPD_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ADPLL_SPD_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ADPLL_SPD_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ADPLL_SPD_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `adpll_spd_in_range_delay` reader - "]
38pub type ADPLL_SPD_IN_RANGE_DELAY_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `adpll_spd_in_range_delay` writer - "]
40pub type ADPLL_SPD_IN_RANGE_DELAY_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
42#[doc = "Field `adpll_spd_out_range_delay` reader - "]
43pub type ADPLL_SPD_OUT_RANGE_DELAY_R = crate::BitReader<bool>;
44#[doc = "Field `adpll_spd_out_range_delay` writer - "]
45pub type ADPLL_SPD_OUT_RANGE_DELAY_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
47#[doc = "Field `adpll_spd_in_range_cons` reader - "]
48pub type ADPLL_SPD_IN_RANGE_CONS_R = crate::FieldReader<u8, u8>;
49#[doc = "Field `adpll_spd_in_range_cons` writer - "]
50pub type ADPLL_SPD_IN_RANGE_CONS_W<'a, const O: u8> =
51 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
52#[doc = "Field `adpll_coarse_path_turnoff` reader - "]
53pub type ADPLL_COARSE_PATH_TURNOFF_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `adpll_coarse_path_turnoff` writer - "]
55pub type ADPLL_COARSE_PATH_TURNOFF_W<'a, const O: u8> =
56 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
57#[doc = "Field `adpll_spd_threshold` reader - "]
58pub type ADPLL_SPD_THRESHOLD_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `adpll_spd_threshold` writer - "]
60pub type ADPLL_SPD_THRESHOLD_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
62#[doc = "Field `adpll_coarse_in_range_cons` reader - "]
63pub type ADPLL_COARSE_IN_RANGE_CONS_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `adpll_coarse_in_range_cons` writer - "]
65pub type ADPLL_COARSE_IN_RANGE_CONS_W<'a, const O: u8> =
66 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
67#[doc = "Field `adpll_spd_gain` reader - "]
68pub type ADPLL_SPD_GAIN_R = crate::FieldReader<u8, u8>;
69#[doc = "Field `adpll_spd_gain` writer - "]
70pub type ADPLL_SPD_GAIN_W<'a, const O: u8> =
71 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
72#[doc = "Field `adpll_coarse_gain` reader - "]
73pub type ADPLL_COARSE_GAIN_R = crate::FieldReader<u8, u8>;
74#[doc = "Field `adpll_coarse_gain` writer - "]
75pub type ADPLL_COARSE_GAIN_W<'a, const O: u8> =
76 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
77#[doc = "Field `adpll_force_lf_fast_mode_ctrl_hw` reader - "]
78pub type ADPLL_FORCE_LF_FAST_MODE_CTRL_HW_R = crate::BitReader<bool>;
79#[doc = "Field `adpll_force_lf_fast_mode_ctrl_hw` writer - "]
80pub type ADPLL_FORCE_LF_FAST_MODE_CTRL_HW_W<'a, const O: u8> =
81 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
82#[doc = "Field `adpll_force_lf_fast_mode` reader - "]
83pub type ADPLL_FORCE_LF_FAST_MODE_R = crate::BitReader<bool>;
84#[doc = "Field `adpll_force_lf_fast_mode` writer - "]
85pub type ADPLL_FORCE_LF_FAST_MODE_W<'a, const O: u8> =
86 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
87#[doc = "Field `adpll_force_lf_fast_mode_hw` reader - "]
88pub type ADPLL_FORCE_LF_FAST_MODE_HW_R = crate::BitReader<bool>;
89#[doc = "Field `adpll_force_lf_fast_mode_hw` writer - "]
90pub type ADPLL_FORCE_LF_FAST_MODE_HW_W<'a, const O: u8> =
91 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
92#[doc = "Field `adpll_coarse_phaerr_en` reader - "]
93pub type ADPLL_COARSE_PHAERR_EN_R = crate::BitReader<bool>;
94#[doc = "Field `adpll_coarse_phaerr_en` writer - "]
95pub type ADPLL_COARSE_PHAERR_EN_W<'a, const O: u8> =
96 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
97#[doc = "Field `adpll_coarse_path_offtime_sel` reader - "]
98pub type ADPLL_COARSE_PATH_OFFTIME_SEL_R = crate::BitReader<bool>;
99#[doc = "Field `adpll_coarse_path_offtime_sel` writer - "]
100pub type ADPLL_COARSE_PATH_OFFTIME_SEL_W<'a, const O: u8> =
101 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
102#[doc = "Field `adpll_spd_outrange_dly_sel_ext` reader - "]
103pub type ADPLL_SPD_OUTRANGE_DLY_SEL_EXT_R = crate::FieldReader<u8, u8>;
104#[doc = "Field `adpll_spd_outrange_dly_sel_ext` writer - "]
105pub type ADPLL_SPD_OUTRANGE_DLY_SEL_EXT_W<'a, const O: u8> =
106 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
107#[doc = "Field `adpll_spd_lms_sstp_win_sel` reader - "]
108pub type ADPLL_SPD_LMS_SSTP_WIN_SEL_R = crate::BitReader<bool>;
109#[doc = "Field `adpll_spd_lms_sstp_win_sel` writer - "]
110pub type ADPLL_SPD_LMS_SSTP_WIN_SEL_W<'a, const O: u8> =
111 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
112#[doc = "Field `adpll_force_coarse_path_on` reader - "]
113pub type ADPLL_FORCE_COARSE_PATH_ON_R = crate::BitReader<bool>;
114#[doc = "Field `adpll_force_coarse_path_on` writer - "]
115pub type ADPLL_FORCE_COARSE_PATH_ON_W<'a, const O: u8> =
116 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
117#[doc = "Field `adpll_coarsepha_dly_sel` reader - "]
118pub type ADPLL_COARSEPHA_DLY_SEL_R = crate::BitReader<bool>;
119#[doc = "Field `adpll_coarsepha_dly_sel` writer - "]
120pub type ADPLL_COARSEPHA_DLY_SEL_W<'a, const O: u8> =
121 crate::BitWriter<'a, u32, ADPLL_SPD_SPEC, bool, O>;
122#[doc = "Field `adpll_spd_in_range_delay_1` reader - "]
123pub type ADPLL_SPD_IN_RANGE_DELAY_1_R = crate::FieldReader<u8, u8>;
124#[doc = "Field `adpll_spd_in_range_delay_1` writer - "]
125pub type ADPLL_SPD_IN_RANGE_DELAY_1_W<'a, const O: u8> =
126 crate::FieldWriter<'a, u32, ADPLL_SPD_SPEC, u8, u8, 2, O>;
127impl R {
128 #[doc = "Bits 0:1"]
129 #[inline(always)]
130 pub fn adpll_spd_in_range_delay(&self) -> ADPLL_SPD_IN_RANGE_DELAY_R {
131 ADPLL_SPD_IN_RANGE_DELAY_R::new((self.bits & 3) as u8)
132 }
133 #[doc = "Bit 4"]
134 #[inline(always)]
135 pub fn adpll_spd_out_range_delay(&self) -> ADPLL_SPD_OUT_RANGE_DELAY_R {
136 ADPLL_SPD_OUT_RANGE_DELAY_R::new(((self.bits >> 4) & 1) != 0)
137 }
138 #[doc = "Bits 8:9"]
139 #[inline(always)]
140 pub fn adpll_spd_in_range_cons(&self) -> ADPLL_SPD_IN_RANGE_CONS_R {
141 ADPLL_SPD_IN_RANGE_CONS_R::new(((self.bits >> 8) & 3) as u8)
142 }
143 #[doc = "Bits 10:11"]
144 #[inline(always)]
145 pub fn adpll_coarse_path_turnoff(&self) -> ADPLL_COARSE_PATH_TURNOFF_R {
146 ADPLL_COARSE_PATH_TURNOFF_R::new(((self.bits >> 10) & 3) as u8)
147 }
148 #[doc = "Bits 12:13"]
149 #[inline(always)]
150 pub fn adpll_spd_threshold(&self) -> ADPLL_SPD_THRESHOLD_R {
151 ADPLL_SPD_THRESHOLD_R::new(((self.bits >> 12) & 3) as u8)
152 }
153 #[doc = "Bits 14:15"]
154 #[inline(always)]
155 pub fn adpll_coarse_in_range_cons(&self) -> ADPLL_COARSE_IN_RANGE_CONS_R {
156 ADPLL_COARSE_IN_RANGE_CONS_R::new(((self.bits >> 14) & 3) as u8)
157 }
158 #[doc = "Bits 16:17"]
159 #[inline(always)]
160 pub fn adpll_spd_gain(&self) -> ADPLL_SPD_GAIN_R {
161 ADPLL_SPD_GAIN_R::new(((self.bits >> 16) & 3) as u8)
162 }
163 #[doc = "Bits 18:19"]
164 #[inline(always)]
165 pub fn adpll_coarse_gain(&self) -> ADPLL_COARSE_GAIN_R {
166 ADPLL_COARSE_GAIN_R::new(((self.bits >> 18) & 3) as u8)
167 }
168 #[doc = "Bit 20"]
169 #[inline(always)]
170 pub fn adpll_force_lf_fast_mode_ctrl_hw(&self) -> ADPLL_FORCE_LF_FAST_MODE_CTRL_HW_R {
171 ADPLL_FORCE_LF_FAST_MODE_CTRL_HW_R::new(((self.bits >> 20) & 1) != 0)
172 }
173 #[doc = "Bit 21"]
174 #[inline(always)]
175 pub fn adpll_force_lf_fast_mode(&self) -> ADPLL_FORCE_LF_FAST_MODE_R {
176 ADPLL_FORCE_LF_FAST_MODE_R::new(((self.bits >> 21) & 1) != 0)
177 }
178 #[doc = "Bit 22"]
179 #[inline(always)]
180 pub fn adpll_force_lf_fast_mode_hw(&self) -> ADPLL_FORCE_LF_FAST_MODE_HW_R {
181 ADPLL_FORCE_LF_FAST_MODE_HW_R::new(((self.bits >> 22) & 1) != 0)
182 }
183 #[doc = "Bit 23"]
184 #[inline(always)]
185 pub fn adpll_coarse_phaerr_en(&self) -> ADPLL_COARSE_PHAERR_EN_R {
186 ADPLL_COARSE_PHAERR_EN_R::new(((self.bits >> 23) & 1) != 0)
187 }
188 #[doc = "Bit 24"]
189 #[inline(always)]
190 pub fn adpll_coarse_path_offtime_sel(&self) -> ADPLL_COARSE_PATH_OFFTIME_SEL_R {
191 ADPLL_COARSE_PATH_OFFTIME_SEL_R::new(((self.bits >> 24) & 1) != 0)
192 }
193 #[doc = "Bits 25:26"]
194 #[inline(always)]
195 pub fn adpll_spd_outrange_dly_sel_ext(&self) -> ADPLL_SPD_OUTRANGE_DLY_SEL_EXT_R {
196 ADPLL_SPD_OUTRANGE_DLY_SEL_EXT_R::new(((self.bits >> 25) & 3) as u8)
197 }
198 #[doc = "Bit 27"]
199 #[inline(always)]
200 pub fn adpll_spd_lms_sstp_win_sel(&self) -> ADPLL_SPD_LMS_SSTP_WIN_SEL_R {
201 ADPLL_SPD_LMS_SSTP_WIN_SEL_R::new(((self.bits >> 27) & 1) != 0)
202 }
203 #[doc = "Bit 28"]
204 #[inline(always)]
205 pub fn adpll_force_coarse_path_on(&self) -> ADPLL_FORCE_COARSE_PATH_ON_R {
206 ADPLL_FORCE_COARSE_PATH_ON_R::new(((self.bits >> 28) & 1) != 0)
207 }
208 #[doc = "Bit 29"]
209 #[inline(always)]
210 pub fn adpll_coarsepha_dly_sel(&self) -> ADPLL_COARSEPHA_DLY_SEL_R {
211 ADPLL_COARSEPHA_DLY_SEL_R::new(((self.bits >> 29) & 1) != 0)
212 }
213 #[doc = "Bits 30:31"]
214 #[inline(always)]
215 pub fn adpll_spd_in_range_delay_1(&self) -> ADPLL_SPD_IN_RANGE_DELAY_1_R {
216 ADPLL_SPD_IN_RANGE_DELAY_1_R::new(((self.bits >> 30) & 3) as u8)
217 }
218}
219impl W {
220 #[doc = "Bits 0:1"]
221 #[inline(always)]
222 #[must_use]
223 pub fn adpll_spd_in_range_delay(&mut self) -> ADPLL_SPD_IN_RANGE_DELAY_W<0> {
224 ADPLL_SPD_IN_RANGE_DELAY_W::new(self)
225 }
226 #[doc = "Bit 4"]
227 #[inline(always)]
228 #[must_use]
229 pub fn adpll_spd_out_range_delay(&mut self) -> ADPLL_SPD_OUT_RANGE_DELAY_W<4> {
230 ADPLL_SPD_OUT_RANGE_DELAY_W::new(self)
231 }
232 #[doc = "Bits 8:9"]
233 #[inline(always)]
234 #[must_use]
235 pub fn adpll_spd_in_range_cons(&mut self) -> ADPLL_SPD_IN_RANGE_CONS_W<8> {
236 ADPLL_SPD_IN_RANGE_CONS_W::new(self)
237 }
238 #[doc = "Bits 10:11"]
239 #[inline(always)]
240 #[must_use]
241 pub fn adpll_coarse_path_turnoff(&mut self) -> ADPLL_COARSE_PATH_TURNOFF_W<10> {
242 ADPLL_COARSE_PATH_TURNOFF_W::new(self)
243 }
244 #[doc = "Bits 12:13"]
245 #[inline(always)]
246 #[must_use]
247 pub fn adpll_spd_threshold(&mut self) -> ADPLL_SPD_THRESHOLD_W<12> {
248 ADPLL_SPD_THRESHOLD_W::new(self)
249 }
250 #[doc = "Bits 14:15"]
251 #[inline(always)]
252 #[must_use]
253 pub fn adpll_coarse_in_range_cons(&mut self) -> ADPLL_COARSE_IN_RANGE_CONS_W<14> {
254 ADPLL_COARSE_IN_RANGE_CONS_W::new(self)
255 }
256 #[doc = "Bits 16:17"]
257 #[inline(always)]
258 #[must_use]
259 pub fn adpll_spd_gain(&mut self) -> ADPLL_SPD_GAIN_W<16> {
260 ADPLL_SPD_GAIN_W::new(self)
261 }
262 #[doc = "Bits 18:19"]
263 #[inline(always)]
264 #[must_use]
265 pub fn adpll_coarse_gain(&mut self) -> ADPLL_COARSE_GAIN_W<18> {
266 ADPLL_COARSE_GAIN_W::new(self)
267 }
268 #[doc = "Bit 20"]
269 #[inline(always)]
270 #[must_use]
271 pub fn adpll_force_lf_fast_mode_ctrl_hw(&mut self) -> ADPLL_FORCE_LF_FAST_MODE_CTRL_HW_W<20> {
272 ADPLL_FORCE_LF_FAST_MODE_CTRL_HW_W::new(self)
273 }
274 #[doc = "Bit 21"]
275 #[inline(always)]
276 #[must_use]
277 pub fn adpll_force_lf_fast_mode(&mut self) -> ADPLL_FORCE_LF_FAST_MODE_W<21> {
278 ADPLL_FORCE_LF_FAST_MODE_W::new(self)
279 }
280 #[doc = "Bit 22"]
281 #[inline(always)]
282 #[must_use]
283 pub fn adpll_force_lf_fast_mode_hw(&mut self) -> ADPLL_FORCE_LF_FAST_MODE_HW_W<22> {
284 ADPLL_FORCE_LF_FAST_MODE_HW_W::new(self)
285 }
286 #[doc = "Bit 23"]
287 #[inline(always)]
288 #[must_use]
289 pub fn adpll_coarse_phaerr_en(&mut self) -> ADPLL_COARSE_PHAERR_EN_W<23> {
290 ADPLL_COARSE_PHAERR_EN_W::new(self)
291 }
292 #[doc = "Bit 24"]
293 #[inline(always)]
294 #[must_use]
295 pub fn adpll_coarse_path_offtime_sel(&mut self) -> ADPLL_COARSE_PATH_OFFTIME_SEL_W<24> {
296 ADPLL_COARSE_PATH_OFFTIME_SEL_W::new(self)
297 }
298 #[doc = "Bits 25:26"]
299 #[inline(always)]
300 #[must_use]
301 pub fn adpll_spd_outrange_dly_sel_ext(&mut self) -> ADPLL_SPD_OUTRANGE_DLY_SEL_EXT_W<25> {
302 ADPLL_SPD_OUTRANGE_DLY_SEL_EXT_W::new(self)
303 }
304 #[doc = "Bit 27"]
305 #[inline(always)]
306 #[must_use]
307 pub fn adpll_spd_lms_sstp_win_sel(&mut self) -> ADPLL_SPD_LMS_SSTP_WIN_SEL_W<27> {
308 ADPLL_SPD_LMS_SSTP_WIN_SEL_W::new(self)
309 }
310 #[doc = "Bit 28"]
311 #[inline(always)]
312 #[must_use]
313 pub fn adpll_force_coarse_path_on(&mut self) -> ADPLL_FORCE_COARSE_PATH_ON_W<28> {
314 ADPLL_FORCE_COARSE_PATH_ON_W::new(self)
315 }
316 #[doc = "Bit 29"]
317 #[inline(always)]
318 #[must_use]
319 pub fn adpll_coarsepha_dly_sel(&mut self) -> ADPLL_COARSEPHA_DLY_SEL_W<29> {
320 ADPLL_COARSEPHA_DLY_SEL_W::new(self)
321 }
322 #[doc = "Bits 30:31"]
323 #[inline(always)]
324 #[must_use]
325 pub fn adpll_spd_in_range_delay_1(&mut self) -> ADPLL_SPD_IN_RANGE_DELAY_1_W<30> {
326 ADPLL_SPD_IN_RANGE_DELAY_1_W::new(self)
327 }
328 #[doc = "Writes raw bits to the register."]
329 #[inline(always)]
330 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
331 self.0.bits(bits);
332 self
333 }
334}
335#[doc = "adpll_spd.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adpll_spd](index.html) module"]
336pub struct ADPLL_SPD_SPEC;
337impl crate::RegisterSpec for ADPLL_SPD_SPEC {
338 type Ux = u32;
339}
340#[doc = "`read()` method returns [adpll_spd::R](R) reader structure"]
341impl crate::Readable for ADPLL_SPD_SPEC {
342 type Reader = R;
343}
344#[doc = "`write(|w| ..)` method takes [adpll_spd::W](W) writer structure"]
345impl crate::Writable for ADPLL_SPD_SPEC {
346 type Writer = W;
347 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
348 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
349}
350#[doc = "`reset()` method sets adpll_spd to value 0"]
351impl crate::Resettable for ADPLL_SPD_SPEC {
352 const RESET_VALUE: Self::Ux = 0;
353}