bl702_pac/rf/
adpll_adc.rs1#[doc = "Register `adpll_adc` reader"]
2pub struct R(crate::R<ADPLL_ADC_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<ADPLL_ADC_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<ADPLL_ADC_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<ADPLL_ADC_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `adpll_adc` writer"]
17pub struct W(crate::W<ADPLL_ADC_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<ADPLL_ADC_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<ADPLL_ADC_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<ADPLL_ADC_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `adpll_adc_vth_bias_mode` reader - "]
38pub type ADPLL_ADC_VTH_BIAS_MODE_R = crate::BitReader<bool>;
39#[doc = "Field `adpll_adc_vth_bias_mode` writer - "]
40pub type ADPLL_ADC_VTH_BIAS_MODE_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
42#[doc = "Field `adpll_adc_vth_en` reader - "]
43pub type ADPLL_ADC_VTH_EN_R = crate::BitReader<bool>;
44#[doc = "Field `adpll_adc_vth_en` writer - "]
45pub type ADPLL_ADC_VTH_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
46#[doc = "Field `adpll_adc_data_sign_sel` reader - "]
47pub type ADPLL_ADC_DATA_SIGN_SEL_R = crate::BitReader<bool>;
48#[doc = "Field `adpll_adc_data_sign_sel` writer - "]
49pub type ADPLL_ADC_DATA_SIGN_SEL_W<'a, const O: u8> =
50 crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
51#[doc = "Field `adpll_adc_vref_fine` reader - "]
52pub type ADPLL_ADC_VREF_FINE_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `adpll_adc_vref_fine` writer - "]
54pub type ADPLL_ADC_VREF_FINE_W<'a, const O: u8> =
55 crate::FieldWriter<'a, u32, ADPLL_ADC_SPEC, u8, u8, 2, O>;
56#[doc = "Field `adpll_adc_vref_coarse` reader - "]
57pub type ADPLL_ADC_VREF_COARSE_R = crate::FieldReader<u8, u8>;
58#[doc = "Field `adpll_adc_vref_coarse` writer - "]
59pub type ADPLL_ADC_VREF_COARSE_W<'a, const O: u8> =
60 crate::FieldWriter<'a, u32, ADPLL_ADC_SPEC, u8, u8, 2, O>;
61#[doc = "Field `adpll_adc_oscal_en` reader - "]
62pub type ADPLL_ADC_OSCAL_EN_R = crate::BitReader<bool>;
63#[doc = "Field `adpll_adc_oscal_en` writer - "]
64pub type ADPLL_ADC_OSCAL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
65#[doc = "Field `adpll_adc_clk_sync_inv` reader - "]
66pub type ADPLL_ADC_CLK_SYNC_INV_R = crate::BitReader<bool>;
67#[doc = "Field `adpll_adc_clk_sync_inv` writer - "]
68pub type ADPLL_ADC_CLK_SYNC_INV_W<'a, const O: u8> =
69 crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
70#[doc = "Field `adpll_adc_clk_div_sel` reader - "]
71pub type ADPLL_ADC_CLK_DIV_SEL_R = crate::BitReader<bool>;
72#[doc = "Field `adpll_adc_clk_div_sel` writer - "]
73pub type ADPLL_ADC_CLK_DIV_SEL_W<'a, const O: u8> =
74 crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
75#[doc = "Field `adpll_adc_clk_inv` reader - "]
76pub type ADPLL_ADC_CLK_INV_R = crate::BitReader<bool>;
77#[doc = "Field `adpll_adc_clk_inv` writer - "]
78pub type ADPLL_ADC_CLK_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
79#[doc = "Field `adpll_adc_clk_en` reader - "]
80pub type ADPLL_ADC_CLK_EN_R = crate::BitReader<bool>;
81#[doc = "Field `adpll_adc_clk_en` writer - "]
82pub type ADPLL_ADC_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADPLL_ADC_SPEC, bool, O>;
83impl R {
84 #[doc = "Bit 0"]
85 #[inline(always)]
86 pub fn adpll_adc_vth_bias_mode(&self) -> ADPLL_ADC_VTH_BIAS_MODE_R {
87 ADPLL_ADC_VTH_BIAS_MODE_R::new((self.bits & 1) != 0)
88 }
89 #[doc = "Bit 1"]
90 #[inline(always)]
91 pub fn adpll_adc_vth_en(&self) -> ADPLL_ADC_VTH_EN_R {
92 ADPLL_ADC_VTH_EN_R::new(((self.bits >> 1) & 1) != 0)
93 }
94 #[doc = "Bit 2"]
95 #[inline(always)]
96 pub fn adpll_adc_data_sign_sel(&self) -> ADPLL_ADC_DATA_SIGN_SEL_R {
97 ADPLL_ADC_DATA_SIGN_SEL_R::new(((self.bits >> 2) & 1) != 0)
98 }
99 #[doc = "Bits 4:5"]
100 #[inline(always)]
101 pub fn adpll_adc_vref_fine(&self) -> ADPLL_ADC_VREF_FINE_R {
102 ADPLL_ADC_VREF_FINE_R::new(((self.bits >> 4) & 3) as u8)
103 }
104 #[doc = "Bits 8:9"]
105 #[inline(always)]
106 pub fn adpll_adc_vref_coarse(&self) -> ADPLL_ADC_VREF_COARSE_R {
107 ADPLL_ADC_VREF_COARSE_R::new(((self.bits >> 8) & 3) as u8)
108 }
109 #[doc = "Bit 12"]
110 #[inline(always)]
111 pub fn adpll_adc_oscal_en(&self) -> ADPLL_ADC_OSCAL_EN_R {
112 ADPLL_ADC_OSCAL_EN_R::new(((self.bits >> 12) & 1) != 0)
113 }
114 #[doc = "Bit 16"]
115 #[inline(always)]
116 pub fn adpll_adc_clk_sync_inv(&self) -> ADPLL_ADC_CLK_SYNC_INV_R {
117 ADPLL_ADC_CLK_SYNC_INV_R::new(((self.bits >> 16) & 1) != 0)
118 }
119 #[doc = "Bit 24"]
120 #[inline(always)]
121 pub fn adpll_adc_clk_div_sel(&self) -> ADPLL_ADC_CLK_DIV_SEL_R {
122 ADPLL_ADC_CLK_DIV_SEL_R::new(((self.bits >> 24) & 1) != 0)
123 }
124 #[doc = "Bit 28"]
125 #[inline(always)]
126 pub fn adpll_adc_clk_inv(&self) -> ADPLL_ADC_CLK_INV_R {
127 ADPLL_ADC_CLK_INV_R::new(((self.bits >> 28) & 1) != 0)
128 }
129 #[doc = "Bit 29"]
130 #[inline(always)]
131 pub fn adpll_adc_clk_en(&self) -> ADPLL_ADC_CLK_EN_R {
132 ADPLL_ADC_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
133 }
134}
135impl W {
136 #[doc = "Bit 0"]
137 #[inline(always)]
138 #[must_use]
139 pub fn adpll_adc_vth_bias_mode(&mut self) -> ADPLL_ADC_VTH_BIAS_MODE_W<0> {
140 ADPLL_ADC_VTH_BIAS_MODE_W::new(self)
141 }
142 #[doc = "Bit 1"]
143 #[inline(always)]
144 #[must_use]
145 pub fn adpll_adc_vth_en(&mut self) -> ADPLL_ADC_VTH_EN_W<1> {
146 ADPLL_ADC_VTH_EN_W::new(self)
147 }
148 #[doc = "Bit 2"]
149 #[inline(always)]
150 #[must_use]
151 pub fn adpll_adc_data_sign_sel(&mut self) -> ADPLL_ADC_DATA_SIGN_SEL_W<2> {
152 ADPLL_ADC_DATA_SIGN_SEL_W::new(self)
153 }
154 #[doc = "Bits 4:5"]
155 #[inline(always)]
156 #[must_use]
157 pub fn adpll_adc_vref_fine(&mut self) -> ADPLL_ADC_VREF_FINE_W<4> {
158 ADPLL_ADC_VREF_FINE_W::new(self)
159 }
160 #[doc = "Bits 8:9"]
161 #[inline(always)]
162 #[must_use]
163 pub fn adpll_adc_vref_coarse(&mut self) -> ADPLL_ADC_VREF_COARSE_W<8> {
164 ADPLL_ADC_VREF_COARSE_W::new(self)
165 }
166 #[doc = "Bit 12"]
167 #[inline(always)]
168 #[must_use]
169 pub fn adpll_adc_oscal_en(&mut self) -> ADPLL_ADC_OSCAL_EN_W<12> {
170 ADPLL_ADC_OSCAL_EN_W::new(self)
171 }
172 #[doc = "Bit 16"]
173 #[inline(always)]
174 #[must_use]
175 pub fn adpll_adc_clk_sync_inv(&mut self) -> ADPLL_ADC_CLK_SYNC_INV_W<16> {
176 ADPLL_ADC_CLK_SYNC_INV_W::new(self)
177 }
178 #[doc = "Bit 24"]
179 #[inline(always)]
180 #[must_use]
181 pub fn adpll_adc_clk_div_sel(&mut self) -> ADPLL_ADC_CLK_DIV_SEL_W<24> {
182 ADPLL_ADC_CLK_DIV_SEL_W::new(self)
183 }
184 #[doc = "Bit 28"]
185 #[inline(always)]
186 #[must_use]
187 pub fn adpll_adc_clk_inv(&mut self) -> ADPLL_ADC_CLK_INV_W<28> {
188 ADPLL_ADC_CLK_INV_W::new(self)
189 }
190 #[doc = "Bit 29"]
191 #[inline(always)]
192 #[must_use]
193 pub fn adpll_adc_clk_en(&mut self) -> ADPLL_ADC_CLK_EN_W<29> {
194 ADPLL_ADC_CLK_EN_W::new(self)
195 }
196 #[doc = "Writes raw bits to the register."]
197 #[inline(always)]
198 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
199 self.0.bits(bits);
200 self
201 }
202}
203#[doc = "adpll_adc.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adpll_adc](index.html) module"]
204pub struct ADPLL_ADC_SPEC;
205impl crate::RegisterSpec for ADPLL_ADC_SPEC {
206 type Ux = u32;
207}
208#[doc = "`read()` method returns [adpll_adc::R](R) reader structure"]
209impl crate::Readable for ADPLL_ADC_SPEC {
210 type Reader = R;
211}
212#[doc = "`write(|w| ..)` method takes [adpll_adc::W](W) writer structure"]
213impl crate::Writable for ADPLL_ADC_SPEC {
214 type Writer = W;
215 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
216 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
217}
218#[doc = "`reset()` method sets adpll_adc to value 0"]
219impl crate::Resettable for ADPLL_ADC_SPEC {
220 const RESET_VALUE: Self::Ux = 0;
221}