1#[doc = "Register `PDS_CTL4` reader"]
2pub struct R(crate::R<PDS_CTL4_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PDS_CTL4_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PDS_CTL4_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PDS_CTL4_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PDS_CTL4` writer"]
17pub struct W(crate::W<PDS_CTL4_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PDS_CTL4_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PDS_CTL4_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PDS_CTL4_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `cr_pds_np_pwr_off` reader - "]
38pub type CR_PDS_NP_PWR_OFF_R = crate::BitReader<bool>;
39#[doc = "Field `cr_pds_np_pwr_off` writer - "]
40pub type CR_PDS_NP_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
41#[doc = "Field `cr_pds_np_reset` reader - "]
42pub type CR_PDS_NP_RESET_R = crate::BitReader<bool>;
43#[doc = "Field `cr_pds_np_reset` writer - "]
44pub type CR_PDS_NP_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
45#[doc = "Field `cr_pds_np_mem_stby` reader - "]
46pub type CR_PDS_NP_MEM_STBY_R = crate::BitReader<bool>;
47#[doc = "Field `cr_pds_np_mem_stby` writer - "]
48pub type CR_PDS_NP_MEM_STBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
49#[doc = "Field `cr_pds_np_gate_clk` reader - "]
50pub type CR_PDS_NP_GATE_CLK_R = crate::BitReader<bool>;
51#[doc = "Field `cr_pds_np_gate_clk` writer - "]
52pub type CR_PDS_NP_GATE_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
53#[doc = "Field `cr_pds_bz_pwr_off` reader - "]
54pub type CR_PDS_BZ_PWR_OFF_R = crate::BitReader<bool>;
55#[doc = "Field `cr_pds_bz_pwr_off` writer - "]
56pub type CR_PDS_BZ_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
57#[doc = "Field `cr_pds_bz_reset` reader - "]
58pub type CR_PDS_BZ_RESET_R = crate::BitReader<bool>;
59#[doc = "Field `cr_pds_bz_reset` writer - "]
60pub type CR_PDS_BZ_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
61#[doc = "Field `cr_pds_bz_mem_stby` reader - "]
62pub type CR_PDS_BZ_MEM_STBY_R = crate::BitReader<bool>;
63#[doc = "Field `cr_pds_bz_mem_stby` writer - "]
64pub type CR_PDS_BZ_MEM_STBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
65#[doc = "Field `cr_pds_bz_gate_clk` reader - "]
66pub type CR_PDS_BZ_GATE_CLK_R = crate::BitReader<bool>;
67#[doc = "Field `cr_pds_bz_gate_clk` writer - "]
68pub type CR_PDS_BZ_GATE_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
69#[doc = "Field `cr_pds_ble_pwr_off` reader - "]
70pub type CR_PDS_BLE_PWR_OFF_R = crate::BitReader<bool>;
71#[doc = "Field `cr_pds_ble_pwr_off` writer - "]
72pub type CR_PDS_BLE_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
73#[doc = "Field `cr_pds_ble_reset` reader - "]
74pub type CR_PDS_BLE_RESET_R = crate::BitReader<bool>;
75#[doc = "Field `cr_pds_ble_reset` writer - "]
76pub type CR_PDS_BLE_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
77#[doc = "Field `cr_pds_ble_mem_stby` reader - "]
78pub type CR_PDS_BLE_MEM_STBY_R = crate::BitReader<bool>;
79#[doc = "Field `cr_pds_ble_mem_stby` writer - "]
80pub type CR_PDS_BLE_MEM_STBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
81#[doc = "Field `cr_pds_ble_gate_clk` reader - "]
82pub type CR_PDS_BLE_GATE_CLK_R = crate::BitReader<bool>;
83#[doc = "Field `cr_pds_ble_gate_clk` writer - "]
84pub type CR_PDS_BLE_GATE_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
85#[doc = "Field `cr_pds_usb_pwr_off` reader - "]
86pub type CR_PDS_USB_PWR_OFF_R = crate::BitReader<bool>;
87#[doc = "Field `cr_pds_usb_pwr_off` writer - "]
88pub type CR_PDS_USB_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
89#[doc = "Field `cr_pds_usb_reset` reader - "]
90pub type CR_PDS_USB_RESET_R = crate::BitReader<bool>;
91#[doc = "Field `cr_pds_usb_reset` writer - "]
92pub type CR_PDS_USB_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
93#[doc = "Field `cr_pds_usb_mem_stby` reader - "]
94pub type CR_PDS_USB_MEM_STBY_R = crate::BitReader<bool>;
95#[doc = "Field `cr_pds_usb_mem_stby` writer - "]
96pub type CR_PDS_USB_MEM_STBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
97#[doc = "Field `cr_pds_usb_gate_clk` reader - "]
98pub type CR_PDS_USB_GATE_CLK_R = crate::BitReader<bool>;
99#[doc = "Field `cr_pds_usb_gate_clk` writer - "]
100pub type CR_PDS_USB_GATE_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
101#[doc = "Field `cr_pds_misc_pwr_off` reader - "]
102pub type CR_PDS_MISC_PWR_OFF_R = crate::BitReader<bool>;
103#[doc = "Field `cr_pds_misc_pwr_off` writer - "]
104pub type CR_PDS_MISC_PWR_OFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
105#[doc = "Field `cr_pds_misc_reset` reader - "]
106pub type CR_PDS_MISC_RESET_R = crate::BitReader<bool>;
107#[doc = "Field `cr_pds_misc_reset` writer - "]
108pub type CR_PDS_MISC_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
109#[doc = "Field `cr_pds_misc_mem_stby` reader - "]
110pub type CR_PDS_MISC_MEM_STBY_R = crate::BitReader<bool>;
111#[doc = "Field `cr_pds_misc_mem_stby` writer - "]
112pub type CR_PDS_MISC_MEM_STBY_W<'a, const O: u8> =
113 crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
114#[doc = "Field `cr_pds_misc_gate_clk` reader - "]
115pub type CR_PDS_MISC_GATE_CLK_R = crate::BitReader<bool>;
116#[doc = "Field `cr_pds_misc_gate_clk` writer - "]
117pub type CR_PDS_MISC_GATE_CLK_W<'a, const O: u8> =
118 crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
119#[doc = "Field `cr_pds_misc_ana_pwr_off` reader - "]
120pub type CR_PDS_MISC_ANA_PWR_OFF_R = crate::BitReader<bool>;
121#[doc = "Field `cr_pds_misc_ana_pwr_off` writer - "]
122pub type CR_PDS_MISC_ANA_PWR_OFF_W<'a, const O: u8> =
123 crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
124#[doc = "Field `cr_pds_misc_dig_pwr_off` reader - "]
125pub type CR_PDS_MISC_DIG_PWR_OFF_R = crate::BitReader<bool>;
126#[doc = "Field `cr_pds_misc_dig_pwr_off` writer - "]
127pub type CR_PDS_MISC_DIG_PWR_OFF_W<'a, const O: u8> =
128 crate::BitWriter<'a, u32, PDS_CTL4_SPEC, bool, O>;
129impl R {
130 #[doc = "Bit 0"]
131 #[inline(always)]
132 pub fn cr_pds_np_pwr_off(&self) -> CR_PDS_NP_PWR_OFF_R {
133 CR_PDS_NP_PWR_OFF_R::new((self.bits & 1) != 0)
134 }
135 #[doc = "Bit 1"]
136 #[inline(always)]
137 pub fn cr_pds_np_reset(&self) -> CR_PDS_NP_RESET_R {
138 CR_PDS_NP_RESET_R::new(((self.bits >> 1) & 1) != 0)
139 }
140 #[doc = "Bit 2"]
141 #[inline(always)]
142 pub fn cr_pds_np_mem_stby(&self) -> CR_PDS_NP_MEM_STBY_R {
143 CR_PDS_NP_MEM_STBY_R::new(((self.bits >> 2) & 1) != 0)
144 }
145 #[doc = "Bit 3"]
146 #[inline(always)]
147 pub fn cr_pds_np_gate_clk(&self) -> CR_PDS_NP_GATE_CLK_R {
148 CR_PDS_NP_GATE_CLK_R::new(((self.bits >> 3) & 1) != 0)
149 }
150 #[doc = "Bit 12"]
151 #[inline(always)]
152 pub fn cr_pds_bz_pwr_off(&self) -> CR_PDS_BZ_PWR_OFF_R {
153 CR_PDS_BZ_PWR_OFF_R::new(((self.bits >> 12) & 1) != 0)
154 }
155 #[doc = "Bit 13"]
156 #[inline(always)]
157 pub fn cr_pds_bz_reset(&self) -> CR_PDS_BZ_RESET_R {
158 CR_PDS_BZ_RESET_R::new(((self.bits >> 13) & 1) != 0)
159 }
160 #[doc = "Bit 14"]
161 #[inline(always)]
162 pub fn cr_pds_bz_mem_stby(&self) -> CR_PDS_BZ_MEM_STBY_R {
163 CR_PDS_BZ_MEM_STBY_R::new(((self.bits >> 14) & 1) != 0)
164 }
165 #[doc = "Bit 15"]
166 #[inline(always)]
167 pub fn cr_pds_bz_gate_clk(&self) -> CR_PDS_BZ_GATE_CLK_R {
168 CR_PDS_BZ_GATE_CLK_R::new(((self.bits >> 15) & 1) != 0)
169 }
170 #[doc = "Bit 16"]
171 #[inline(always)]
172 pub fn cr_pds_ble_pwr_off(&self) -> CR_PDS_BLE_PWR_OFF_R {
173 CR_PDS_BLE_PWR_OFF_R::new(((self.bits >> 16) & 1) != 0)
174 }
175 #[doc = "Bit 17"]
176 #[inline(always)]
177 pub fn cr_pds_ble_reset(&self) -> CR_PDS_BLE_RESET_R {
178 CR_PDS_BLE_RESET_R::new(((self.bits >> 17) & 1) != 0)
179 }
180 #[doc = "Bit 18"]
181 #[inline(always)]
182 pub fn cr_pds_ble_mem_stby(&self) -> CR_PDS_BLE_MEM_STBY_R {
183 CR_PDS_BLE_MEM_STBY_R::new(((self.bits >> 18) & 1) != 0)
184 }
185 #[doc = "Bit 19"]
186 #[inline(always)]
187 pub fn cr_pds_ble_gate_clk(&self) -> CR_PDS_BLE_GATE_CLK_R {
188 CR_PDS_BLE_GATE_CLK_R::new(((self.bits >> 19) & 1) != 0)
189 }
190 #[doc = "Bit 20"]
191 #[inline(always)]
192 pub fn cr_pds_usb_pwr_off(&self) -> CR_PDS_USB_PWR_OFF_R {
193 CR_PDS_USB_PWR_OFF_R::new(((self.bits >> 20) & 1) != 0)
194 }
195 #[doc = "Bit 21"]
196 #[inline(always)]
197 pub fn cr_pds_usb_reset(&self) -> CR_PDS_USB_RESET_R {
198 CR_PDS_USB_RESET_R::new(((self.bits >> 21) & 1) != 0)
199 }
200 #[doc = "Bit 22"]
201 #[inline(always)]
202 pub fn cr_pds_usb_mem_stby(&self) -> CR_PDS_USB_MEM_STBY_R {
203 CR_PDS_USB_MEM_STBY_R::new(((self.bits >> 22) & 1) != 0)
204 }
205 #[doc = "Bit 23"]
206 #[inline(always)]
207 pub fn cr_pds_usb_gate_clk(&self) -> CR_PDS_USB_GATE_CLK_R {
208 CR_PDS_USB_GATE_CLK_R::new(((self.bits >> 23) & 1) != 0)
209 }
210 #[doc = "Bit 24"]
211 #[inline(always)]
212 pub fn cr_pds_misc_pwr_off(&self) -> CR_PDS_MISC_PWR_OFF_R {
213 CR_PDS_MISC_PWR_OFF_R::new(((self.bits >> 24) & 1) != 0)
214 }
215 #[doc = "Bit 25"]
216 #[inline(always)]
217 pub fn cr_pds_misc_reset(&self) -> CR_PDS_MISC_RESET_R {
218 CR_PDS_MISC_RESET_R::new(((self.bits >> 25) & 1) != 0)
219 }
220 #[doc = "Bit 26"]
221 #[inline(always)]
222 pub fn cr_pds_misc_mem_stby(&self) -> CR_PDS_MISC_MEM_STBY_R {
223 CR_PDS_MISC_MEM_STBY_R::new(((self.bits >> 26) & 1) != 0)
224 }
225 #[doc = "Bit 27"]
226 #[inline(always)]
227 pub fn cr_pds_misc_gate_clk(&self) -> CR_PDS_MISC_GATE_CLK_R {
228 CR_PDS_MISC_GATE_CLK_R::new(((self.bits >> 27) & 1) != 0)
229 }
230 #[doc = "Bit 30"]
231 #[inline(always)]
232 pub fn cr_pds_misc_ana_pwr_off(&self) -> CR_PDS_MISC_ANA_PWR_OFF_R {
233 CR_PDS_MISC_ANA_PWR_OFF_R::new(((self.bits >> 30) & 1) != 0)
234 }
235 #[doc = "Bit 31"]
236 #[inline(always)]
237 pub fn cr_pds_misc_dig_pwr_off(&self) -> CR_PDS_MISC_DIG_PWR_OFF_R {
238 CR_PDS_MISC_DIG_PWR_OFF_R::new(((self.bits >> 31) & 1) != 0)
239 }
240}
241impl W {
242 #[doc = "Bit 0"]
243 #[inline(always)]
244 #[must_use]
245 pub fn cr_pds_np_pwr_off(&mut self) -> CR_PDS_NP_PWR_OFF_W<0> {
246 CR_PDS_NP_PWR_OFF_W::new(self)
247 }
248 #[doc = "Bit 1"]
249 #[inline(always)]
250 #[must_use]
251 pub fn cr_pds_np_reset(&mut self) -> CR_PDS_NP_RESET_W<1> {
252 CR_PDS_NP_RESET_W::new(self)
253 }
254 #[doc = "Bit 2"]
255 #[inline(always)]
256 #[must_use]
257 pub fn cr_pds_np_mem_stby(&mut self) -> CR_PDS_NP_MEM_STBY_W<2> {
258 CR_PDS_NP_MEM_STBY_W::new(self)
259 }
260 #[doc = "Bit 3"]
261 #[inline(always)]
262 #[must_use]
263 pub fn cr_pds_np_gate_clk(&mut self) -> CR_PDS_NP_GATE_CLK_W<3> {
264 CR_PDS_NP_GATE_CLK_W::new(self)
265 }
266 #[doc = "Bit 12"]
267 #[inline(always)]
268 #[must_use]
269 pub fn cr_pds_bz_pwr_off(&mut self) -> CR_PDS_BZ_PWR_OFF_W<12> {
270 CR_PDS_BZ_PWR_OFF_W::new(self)
271 }
272 #[doc = "Bit 13"]
273 #[inline(always)]
274 #[must_use]
275 pub fn cr_pds_bz_reset(&mut self) -> CR_PDS_BZ_RESET_W<13> {
276 CR_PDS_BZ_RESET_W::new(self)
277 }
278 #[doc = "Bit 14"]
279 #[inline(always)]
280 #[must_use]
281 pub fn cr_pds_bz_mem_stby(&mut self) -> CR_PDS_BZ_MEM_STBY_W<14> {
282 CR_PDS_BZ_MEM_STBY_W::new(self)
283 }
284 #[doc = "Bit 15"]
285 #[inline(always)]
286 #[must_use]
287 pub fn cr_pds_bz_gate_clk(&mut self) -> CR_PDS_BZ_GATE_CLK_W<15> {
288 CR_PDS_BZ_GATE_CLK_W::new(self)
289 }
290 #[doc = "Bit 16"]
291 #[inline(always)]
292 #[must_use]
293 pub fn cr_pds_ble_pwr_off(&mut self) -> CR_PDS_BLE_PWR_OFF_W<16> {
294 CR_PDS_BLE_PWR_OFF_W::new(self)
295 }
296 #[doc = "Bit 17"]
297 #[inline(always)]
298 #[must_use]
299 pub fn cr_pds_ble_reset(&mut self) -> CR_PDS_BLE_RESET_W<17> {
300 CR_PDS_BLE_RESET_W::new(self)
301 }
302 #[doc = "Bit 18"]
303 #[inline(always)]
304 #[must_use]
305 pub fn cr_pds_ble_mem_stby(&mut self) -> CR_PDS_BLE_MEM_STBY_W<18> {
306 CR_PDS_BLE_MEM_STBY_W::new(self)
307 }
308 #[doc = "Bit 19"]
309 #[inline(always)]
310 #[must_use]
311 pub fn cr_pds_ble_gate_clk(&mut self) -> CR_PDS_BLE_GATE_CLK_W<19> {
312 CR_PDS_BLE_GATE_CLK_W::new(self)
313 }
314 #[doc = "Bit 20"]
315 #[inline(always)]
316 #[must_use]
317 pub fn cr_pds_usb_pwr_off(&mut self) -> CR_PDS_USB_PWR_OFF_W<20> {
318 CR_PDS_USB_PWR_OFF_W::new(self)
319 }
320 #[doc = "Bit 21"]
321 #[inline(always)]
322 #[must_use]
323 pub fn cr_pds_usb_reset(&mut self) -> CR_PDS_USB_RESET_W<21> {
324 CR_PDS_USB_RESET_W::new(self)
325 }
326 #[doc = "Bit 22"]
327 #[inline(always)]
328 #[must_use]
329 pub fn cr_pds_usb_mem_stby(&mut self) -> CR_PDS_USB_MEM_STBY_W<22> {
330 CR_PDS_USB_MEM_STBY_W::new(self)
331 }
332 #[doc = "Bit 23"]
333 #[inline(always)]
334 #[must_use]
335 pub fn cr_pds_usb_gate_clk(&mut self) -> CR_PDS_USB_GATE_CLK_W<23> {
336 CR_PDS_USB_GATE_CLK_W::new(self)
337 }
338 #[doc = "Bit 24"]
339 #[inline(always)]
340 #[must_use]
341 pub fn cr_pds_misc_pwr_off(&mut self) -> CR_PDS_MISC_PWR_OFF_W<24> {
342 CR_PDS_MISC_PWR_OFF_W::new(self)
343 }
344 #[doc = "Bit 25"]
345 #[inline(always)]
346 #[must_use]
347 pub fn cr_pds_misc_reset(&mut self) -> CR_PDS_MISC_RESET_W<25> {
348 CR_PDS_MISC_RESET_W::new(self)
349 }
350 #[doc = "Bit 26"]
351 #[inline(always)]
352 #[must_use]
353 pub fn cr_pds_misc_mem_stby(&mut self) -> CR_PDS_MISC_MEM_STBY_W<26> {
354 CR_PDS_MISC_MEM_STBY_W::new(self)
355 }
356 #[doc = "Bit 27"]
357 #[inline(always)]
358 #[must_use]
359 pub fn cr_pds_misc_gate_clk(&mut self) -> CR_PDS_MISC_GATE_CLK_W<27> {
360 CR_PDS_MISC_GATE_CLK_W::new(self)
361 }
362 #[doc = "Bit 30"]
363 #[inline(always)]
364 #[must_use]
365 pub fn cr_pds_misc_ana_pwr_off(&mut self) -> CR_PDS_MISC_ANA_PWR_OFF_W<30> {
366 CR_PDS_MISC_ANA_PWR_OFF_W::new(self)
367 }
368 #[doc = "Bit 31"]
369 #[inline(always)]
370 #[must_use]
371 pub fn cr_pds_misc_dig_pwr_off(&mut self) -> CR_PDS_MISC_DIG_PWR_OFF_W<31> {
372 CR_PDS_MISC_DIG_PWR_OFF_W::new(self)
373 }
374 #[doc = "Writes raw bits to the register."]
375 #[inline(always)]
376 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
377 self.0.bits(bits);
378 self
379 }
380}
381#[doc = "PDS_CTL4.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pds_ctl4](index.html) module"]
382pub struct PDS_CTL4_SPEC;
383impl crate::RegisterSpec for PDS_CTL4_SPEC {
384 type Ux = u32;
385}
386#[doc = "`read()` method returns [pds_ctl4::R](R) reader structure"]
387impl crate::Readable for PDS_CTL4_SPEC {
388 type Reader = R;
389}
390#[doc = "`write(|w| ..)` method takes [pds_ctl4::W](W) writer structure"]
391impl crate::Writable for PDS_CTL4_SPEC {
392 type Writer = W;
393 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
394 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
395}
396#[doc = "`reset()` method sets PDS_CTL4 to value 0"]
397impl crate::Resettable for PDS_CTL4_SPEC {
398 const RESET_VALUE: Self::Ux = 0;
399}