bl702_pac/pds/
clkpll_test_enable.rs1#[doc = "Register `clkpll_test_enable` reader"]
2pub struct R(crate::R<CLKPLL_TEST_ENABLE_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLKPLL_TEST_ENABLE_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLKPLL_TEST_ENABLE_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLKPLL_TEST_ENABLE_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `clkpll_test_enable` writer"]
17pub struct W(crate::W<CLKPLL_TEST_ENABLE_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLKPLL_TEST_ENABLE_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLKPLL_TEST_ENABLE_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLKPLL_TEST_ENABLE_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `dten_clkpll_postdiv_clk` reader - "]
38pub type DTEN_CLKPLL_POSTDIV_CLK_R = crate::BitReader<bool>;
39#[doc = "Field `dten_clkpll_postdiv_clk` writer - "]
40pub type DTEN_CLKPLL_POSTDIV_CLK_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
42#[doc = "Field `dten_clk96M` reader - "]
43pub type DTEN_CLK96M_R = crate::BitReader<bool>;
44#[doc = "Field `dten_clk96M` writer - "]
45pub type DTEN_CLK96M_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
47#[doc = "Field `dten_clk32M` reader - "]
48pub type DTEN_CLK32M_R = crate::BitReader<bool>;
49#[doc = "Field `dten_clk32M` writer - "]
50pub type DTEN_CLK32M_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
52#[doc = "Field `dten_clkpll_fsdm` reader - "]
53pub type DTEN_CLKPLL_FSDM_R = crate::BitReader<bool>;
54#[doc = "Field `dten_clkpll_fsdm` writer - "]
55pub type DTEN_CLKPLL_FSDM_W<'a, const O: u8> =
56 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
57#[doc = "Field `dten_clkpll_fref` reader - "]
58pub type DTEN_CLKPLL_FREF_R = crate::BitReader<bool>;
59#[doc = "Field `dten_clkpll_fref` writer - "]
60pub type DTEN_CLKPLL_FREF_W<'a, const O: u8> =
61 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
62#[doc = "Field `dten_clkpll_fin` reader - "]
63pub type DTEN_CLKPLL_FIN_R = crate::BitReader<bool>;
64#[doc = "Field `dten_clkpll_fin` writer - "]
65pub type DTEN_CLKPLL_FIN_W<'a, const O: u8> =
66 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
67#[doc = "Field `ten_clkpll_sfreg` reader - "]
68pub type TEN_CLKPLL_SFREG_R = crate::BitReader<bool>;
69#[doc = "Field `ten_clkpll_sfreg` writer - "]
70pub type TEN_CLKPLL_SFREG_W<'a, const O: u8> =
71 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
72#[doc = "Field `ten_clkpll` reader - "]
73pub type TEN_CLKPLL_R = crate::BitReader<bool>;
74#[doc = "Field `ten_clkpll` writer - "]
75pub type TEN_CLKPLL_W<'a, const O: u8> =
76 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
77#[doc = "Field `clkpll_dc_tp_out_en` reader - "]
78pub type CLKPLL_DC_TP_OUT_EN_R = crate::BitReader<bool>;
79#[doc = "Field `clkpll_dc_tp_out_en` writer - "]
80pub type CLKPLL_DC_TP_OUT_EN_W<'a, const O: u8> =
81 crate::BitWriter<'a, u32, CLKPLL_TEST_ENABLE_SPEC, bool, O>;
82impl R {
83 #[doc = "Bit 0"]
84 #[inline(always)]
85 pub fn dten_clkpll_postdiv_clk(&self) -> DTEN_CLKPLL_POSTDIV_CLK_R {
86 DTEN_CLKPLL_POSTDIV_CLK_R::new((self.bits & 1) != 0)
87 }
88 #[doc = "Bit 1"]
89 #[inline(always)]
90 pub fn dten_clk96m(&self) -> DTEN_CLK96M_R {
91 DTEN_CLK96M_R::new(((self.bits >> 1) & 1) != 0)
92 }
93 #[doc = "Bit 2"]
94 #[inline(always)]
95 pub fn dten_clk32m(&self) -> DTEN_CLK32M_R {
96 DTEN_CLK32M_R::new(((self.bits >> 2) & 1) != 0)
97 }
98 #[doc = "Bit 3"]
99 #[inline(always)]
100 pub fn dten_clkpll_fsdm(&self) -> DTEN_CLKPLL_FSDM_R {
101 DTEN_CLKPLL_FSDM_R::new(((self.bits >> 3) & 1) != 0)
102 }
103 #[doc = "Bit 4"]
104 #[inline(always)]
105 pub fn dten_clkpll_fref(&self) -> DTEN_CLKPLL_FREF_R {
106 DTEN_CLKPLL_FREF_R::new(((self.bits >> 4) & 1) != 0)
107 }
108 #[doc = "Bit 5"]
109 #[inline(always)]
110 pub fn dten_clkpll_fin(&self) -> DTEN_CLKPLL_FIN_R {
111 DTEN_CLKPLL_FIN_R::new(((self.bits >> 5) & 1) != 0)
112 }
113 #[doc = "Bit 6"]
114 #[inline(always)]
115 pub fn ten_clkpll_sfreg(&self) -> TEN_CLKPLL_SFREG_R {
116 TEN_CLKPLL_SFREG_R::new(((self.bits >> 6) & 1) != 0)
117 }
118 #[doc = "Bit 7"]
119 #[inline(always)]
120 pub fn ten_clkpll(&self) -> TEN_CLKPLL_R {
121 TEN_CLKPLL_R::new(((self.bits >> 7) & 1) != 0)
122 }
123 #[doc = "Bit 8"]
124 #[inline(always)]
125 pub fn clkpll_dc_tp_out_en(&self) -> CLKPLL_DC_TP_OUT_EN_R {
126 CLKPLL_DC_TP_OUT_EN_R::new(((self.bits >> 8) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0"]
131 #[inline(always)]
132 #[must_use]
133 pub fn dten_clkpll_postdiv_clk(&mut self) -> DTEN_CLKPLL_POSTDIV_CLK_W<0> {
134 DTEN_CLKPLL_POSTDIV_CLK_W::new(self)
135 }
136 #[doc = "Bit 1"]
137 #[inline(always)]
138 #[must_use]
139 pub fn dten_clk96m(&mut self) -> DTEN_CLK96M_W<1> {
140 DTEN_CLK96M_W::new(self)
141 }
142 #[doc = "Bit 2"]
143 #[inline(always)]
144 #[must_use]
145 pub fn dten_clk32m(&mut self) -> DTEN_CLK32M_W<2> {
146 DTEN_CLK32M_W::new(self)
147 }
148 #[doc = "Bit 3"]
149 #[inline(always)]
150 #[must_use]
151 pub fn dten_clkpll_fsdm(&mut self) -> DTEN_CLKPLL_FSDM_W<3> {
152 DTEN_CLKPLL_FSDM_W::new(self)
153 }
154 #[doc = "Bit 4"]
155 #[inline(always)]
156 #[must_use]
157 pub fn dten_clkpll_fref(&mut self) -> DTEN_CLKPLL_FREF_W<4> {
158 DTEN_CLKPLL_FREF_W::new(self)
159 }
160 #[doc = "Bit 5"]
161 #[inline(always)]
162 #[must_use]
163 pub fn dten_clkpll_fin(&mut self) -> DTEN_CLKPLL_FIN_W<5> {
164 DTEN_CLKPLL_FIN_W::new(self)
165 }
166 #[doc = "Bit 6"]
167 #[inline(always)]
168 #[must_use]
169 pub fn ten_clkpll_sfreg(&mut self) -> TEN_CLKPLL_SFREG_W<6> {
170 TEN_CLKPLL_SFREG_W::new(self)
171 }
172 #[doc = "Bit 7"]
173 #[inline(always)]
174 #[must_use]
175 pub fn ten_clkpll(&mut self) -> TEN_CLKPLL_W<7> {
176 TEN_CLKPLL_W::new(self)
177 }
178 #[doc = "Bit 8"]
179 #[inline(always)]
180 #[must_use]
181 pub fn clkpll_dc_tp_out_en(&mut self) -> CLKPLL_DC_TP_OUT_EN_W<8> {
182 CLKPLL_DC_TP_OUT_EN_W::new(self)
183 }
184 #[doc = "Writes raw bits to the register."]
185 #[inline(always)]
186 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
187 self.0.bits(bits);
188 self
189 }
190}
191#[doc = "clkpll_test_enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkpll_test_enable](index.html) module"]
192pub struct CLKPLL_TEST_ENABLE_SPEC;
193impl crate::RegisterSpec for CLKPLL_TEST_ENABLE_SPEC {
194 type Ux = u32;
195}
196#[doc = "`read()` method returns [clkpll_test_enable::R](R) reader structure"]
197impl crate::Readable for CLKPLL_TEST_ENABLE_SPEC {
198 type Reader = R;
199}
200#[doc = "`write(|w| ..)` method takes [clkpll_test_enable::W](W) writer structure"]
201impl crate::Writable for CLKPLL_TEST_ENABLE_SPEC {
202 type Writer = W;
203 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
204 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
205}
206#[doc = "`reset()` method sets clkpll_test_enable to value 0"]
207impl crate::Resettable for CLKPLL_TEST_ENABLE_SPEC {
208 const RESET_VALUE: Self::Ux = 0;
209}