1#[doc = "Register `mjpeg_control_1` reader"]
2pub struct R(crate::R<MJPEG_CONTROL_1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<MJPEG_CONTROL_1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<MJPEG_CONTROL_1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<MJPEG_CONTROL_1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `mjpeg_control_1` writer"]
17pub struct W(crate::W<MJPEG_CONTROL_1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<MJPEG_CONTROL_1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<MJPEG_CONTROL_1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<MJPEG_CONTROL_1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `reg_mjpeg_enable` reader - "]
38pub type REG_MJPEG_ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `reg_mjpeg_enable` writer - "]
40pub type REG_MJPEG_ENABLE_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, MJPEG_CONTROL_1_SPEC, bool, O>;
42#[doc = "Field `reg_mjpeg_bit_order` reader - "]
43pub type REG_MJPEG_BIT_ORDER_R = crate::BitReader<bool>;
44#[doc = "Field `reg_mjpeg_bit_order` writer - "]
45pub type REG_MJPEG_BIT_ORDER_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, MJPEG_CONTROL_1_SPEC, bool, O>;
47#[doc = "Field `reg_order_u_even` reader - "]
48pub type REG_ORDER_U_EVEN_R = crate::BitReader<bool>;
49#[doc = "Field `reg_order_u_even` writer - "]
50pub type REG_ORDER_U_EVEN_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, MJPEG_CONTROL_1_SPEC, bool, O>;
52#[doc = "Field `reg_wr_over_stop` reader - "]
53pub type REG_WR_OVER_STOP_R = crate::BitReader<bool>;
54#[doc = "Field `reg_wr_over_stop` writer - "]
55pub type REG_WR_OVER_STOP_W<'a, const O: u8> =
56 crate::BitWriter<'a, u32, MJPEG_CONTROL_1_SPEC, bool, O>;
57#[doc = "Field `reg_last_hf_wblk_dmy` reader - "]
58pub type REG_LAST_HF_WBLK_DMY_R = crate::BitReader<bool>;
59#[doc = "Field `reg_last_hf_wblk_dmy` writer - "]
60pub type REG_LAST_HF_WBLK_DMY_W<'a, const O: u8> =
61 crate::BitWriter<'a, u32, MJPEG_CONTROL_1_SPEC, bool, O>;
62#[doc = "Field `reg_last_hf_hblk_dmy` reader - "]
63pub type REG_LAST_HF_HBLK_DMY_R = crate::BitReader<bool>;
64#[doc = "Field `reg_last_hf_hblk_dmy` writer - "]
65pub type REG_LAST_HF_HBLK_DMY_W<'a, const O: u8> =
66 crate::BitWriter<'a, u32, MJPEG_CONTROL_1_SPEC, bool, O>;
67#[doc = "Field `reg_reflect_dmy` reader - "]
68pub type REG_REFLECT_DMY_R = crate::BitReader<bool>;
69#[doc = "Field `reg_reflect_dmy` writer - "]
70pub type REG_REFLECT_DMY_W<'a, const O: u8> =
71 crate::BitWriter<'a, u32, MJPEG_CONTROL_1_SPEC, bool, O>;
72#[doc = "Field `reg_h_bust` reader - "]
73pub type REG_H_BUST_R = crate::FieldReader<u8, u8>;
74#[doc = "Field `reg_h_bust` writer - "]
75pub type REG_H_BUST_W<'a, const O: u8> =
76 crate::FieldWriter<'a, u32, MJPEG_CONTROL_1_SPEC, u8, u8, 2, O>;
77#[doc = "Field `reg_yuv_mode` reader - "]
78pub type REG_YUV_MODE_R = crate::FieldReader<u8, u8>;
79#[doc = "Field `reg_yuv_mode` writer - "]
80pub type REG_YUV_MODE_W<'a, const O: u8> =
81 crate::FieldWriter<'a, u32, MJPEG_CONTROL_1_SPEC, u8, u8, 2, O>;
82#[doc = "Field `reg_q_mode` reader - "]
83pub type REG_Q_MODE_R = crate::FieldReader<u8, u8>;
84#[doc = "Field `reg_q_mode` writer - "]
85pub type REG_Q_MODE_W<'a, const O: u8> =
86 crate::FieldWriter<'a, u32, MJPEG_CONTROL_1_SPEC, u8, u8, 7, O>;
87#[doc = "Field `reg_y0_order` reader - "]
88pub type REG_Y0_ORDER_R = crate::FieldReader<u8, u8>;
89#[doc = "Field `reg_y0_order` writer - "]
90pub type REG_Y0_ORDER_W<'a, const O: u8> =
91 crate::FieldWriter<'a, u32, MJPEG_CONTROL_1_SPEC, u8, u8, 2, O>;
92#[doc = "Field `reg_u0_order` reader - "]
93pub type REG_U0_ORDER_R = crate::FieldReader<u8, u8>;
94#[doc = "Field `reg_u0_order` writer - "]
95pub type REG_U0_ORDER_W<'a, const O: u8> =
96 crate::FieldWriter<'a, u32, MJPEG_CONTROL_1_SPEC, u8, u8, 2, O>;
97#[doc = "Field `reg_y1_order` reader - "]
98pub type REG_Y1_ORDER_R = crate::FieldReader<u8, u8>;
99#[doc = "Field `reg_y1_order` writer - "]
100pub type REG_Y1_ORDER_W<'a, const O: u8> =
101 crate::FieldWriter<'a, u32, MJPEG_CONTROL_1_SPEC, u8, u8, 2, O>;
102#[doc = "Field `reg_v0_order` reader - "]
103pub type REG_V0_ORDER_R = crate::FieldReader<u8, u8>;
104#[doc = "Field `reg_v0_order` writer - "]
105pub type REG_V0_ORDER_W<'a, const O: u8> =
106 crate::FieldWriter<'a, u32, MJPEG_CONTROL_1_SPEC, u8, u8, 2, O>;
107impl R {
108 #[doc = "Bit 0"]
109 #[inline(always)]
110 pub fn reg_mjpeg_enable(&self) -> REG_MJPEG_ENABLE_R {
111 REG_MJPEG_ENABLE_R::new((self.bits & 1) != 0)
112 }
113 #[doc = "Bit 1"]
114 #[inline(always)]
115 pub fn reg_mjpeg_bit_order(&self) -> REG_MJPEG_BIT_ORDER_R {
116 REG_MJPEG_BIT_ORDER_R::new(((self.bits >> 1) & 1) != 0)
117 }
118 #[doc = "Bit 2"]
119 #[inline(always)]
120 pub fn reg_order_u_even(&self) -> REG_ORDER_U_EVEN_R {
121 REG_ORDER_U_EVEN_R::new(((self.bits >> 2) & 1) != 0)
122 }
123 #[doc = "Bit 3"]
124 #[inline(always)]
125 pub fn reg_wr_over_stop(&self) -> REG_WR_OVER_STOP_R {
126 REG_WR_OVER_STOP_R::new(((self.bits >> 3) & 1) != 0)
127 }
128 #[doc = "Bit 4"]
129 #[inline(always)]
130 pub fn reg_last_hf_wblk_dmy(&self) -> REG_LAST_HF_WBLK_DMY_R {
131 REG_LAST_HF_WBLK_DMY_R::new(((self.bits >> 4) & 1) != 0)
132 }
133 #[doc = "Bit 5"]
134 #[inline(always)]
135 pub fn reg_last_hf_hblk_dmy(&self) -> REG_LAST_HF_HBLK_DMY_R {
136 REG_LAST_HF_HBLK_DMY_R::new(((self.bits >> 5) & 1) != 0)
137 }
138 #[doc = "Bit 6"]
139 #[inline(always)]
140 pub fn reg_reflect_dmy(&self) -> REG_REFLECT_DMY_R {
141 REG_REFLECT_DMY_R::new(((self.bits >> 6) & 1) != 0)
142 }
143 #[doc = "Bits 8:9"]
144 #[inline(always)]
145 pub fn reg_h_bust(&self) -> REG_H_BUST_R {
146 REG_H_BUST_R::new(((self.bits >> 8) & 3) as u8)
147 }
148 #[doc = "Bits 12:13"]
149 #[inline(always)]
150 pub fn reg_yuv_mode(&self) -> REG_YUV_MODE_R {
151 REG_YUV_MODE_R::new(((self.bits >> 12) & 3) as u8)
152 }
153 #[doc = "Bits 16:22"]
154 #[inline(always)]
155 pub fn reg_q_mode(&self) -> REG_Q_MODE_R {
156 REG_Q_MODE_R::new(((self.bits >> 16) & 0x7f) as u8)
157 }
158 #[doc = "Bits 24:25"]
159 #[inline(always)]
160 pub fn reg_y0_order(&self) -> REG_Y0_ORDER_R {
161 REG_Y0_ORDER_R::new(((self.bits >> 24) & 3) as u8)
162 }
163 #[doc = "Bits 26:27"]
164 #[inline(always)]
165 pub fn reg_u0_order(&self) -> REG_U0_ORDER_R {
166 REG_U0_ORDER_R::new(((self.bits >> 26) & 3) as u8)
167 }
168 #[doc = "Bits 28:29"]
169 #[inline(always)]
170 pub fn reg_y1_order(&self) -> REG_Y1_ORDER_R {
171 REG_Y1_ORDER_R::new(((self.bits >> 28) & 3) as u8)
172 }
173 #[doc = "Bits 30:31"]
174 #[inline(always)]
175 pub fn reg_v0_order(&self) -> REG_V0_ORDER_R {
176 REG_V0_ORDER_R::new(((self.bits >> 30) & 3) as u8)
177 }
178}
179impl W {
180 #[doc = "Bit 0"]
181 #[inline(always)]
182 #[must_use]
183 pub fn reg_mjpeg_enable(&mut self) -> REG_MJPEG_ENABLE_W<0> {
184 REG_MJPEG_ENABLE_W::new(self)
185 }
186 #[doc = "Bit 1"]
187 #[inline(always)]
188 #[must_use]
189 pub fn reg_mjpeg_bit_order(&mut self) -> REG_MJPEG_BIT_ORDER_W<1> {
190 REG_MJPEG_BIT_ORDER_W::new(self)
191 }
192 #[doc = "Bit 2"]
193 #[inline(always)]
194 #[must_use]
195 pub fn reg_order_u_even(&mut self) -> REG_ORDER_U_EVEN_W<2> {
196 REG_ORDER_U_EVEN_W::new(self)
197 }
198 #[doc = "Bit 3"]
199 #[inline(always)]
200 #[must_use]
201 pub fn reg_wr_over_stop(&mut self) -> REG_WR_OVER_STOP_W<3> {
202 REG_WR_OVER_STOP_W::new(self)
203 }
204 #[doc = "Bit 4"]
205 #[inline(always)]
206 #[must_use]
207 pub fn reg_last_hf_wblk_dmy(&mut self) -> REG_LAST_HF_WBLK_DMY_W<4> {
208 REG_LAST_HF_WBLK_DMY_W::new(self)
209 }
210 #[doc = "Bit 5"]
211 #[inline(always)]
212 #[must_use]
213 pub fn reg_last_hf_hblk_dmy(&mut self) -> REG_LAST_HF_HBLK_DMY_W<5> {
214 REG_LAST_HF_HBLK_DMY_W::new(self)
215 }
216 #[doc = "Bit 6"]
217 #[inline(always)]
218 #[must_use]
219 pub fn reg_reflect_dmy(&mut self) -> REG_REFLECT_DMY_W<6> {
220 REG_REFLECT_DMY_W::new(self)
221 }
222 #[doc = "Bits 8:9"]
223 #[inline(always)]
224 #[must_use]
225 pub fn reg_h_bust(&mut self) -> REG_H_BUST_W<8> {
226 REG_H_BUST_W::new(self)
227 }
228 #[doc = "Bits 12:13"]
229 #[inline(always)]
230 #[must_use]
231 pub fn reg_yuv_mode(&mut self) -> REG_YUV_MODE_W<12> {
232 REG_YUV_MODE_W::new(self)
233 }
234 #[doc = "Bits 16:22"]
235 #[inline(always)]
236 #[must_use]
237 pub fn reg_q_mode(&mut self) -> REG_Q_MODE_W<16> {
238 REG_Q_MODE_W::new(self)
239 }
240 #[doc = "Bits 24:25"]
241 #[inline(always)]
242 #[must_use]
243 pub fn reg_y0_order(&mut self) -> REG_Y0_ORDER_W<24> {
244 REG_Y0_ORDER_W::new(self)
245 }
246 #[doc = "Bits 26:27"]
247 #[inline(always)]
248 #[must_use]
249 pub fn reg_u0_order(&mut self) -> REG_U0_ORDER_W<26> {
250 REG_U0_ORDER_W::new(self)
251 }
252 #[doc = "Bits 28:29"]
253 #[inline(always)]
254 #[must_use]
255 pub fn reg_y1_order(&mut self) -> REG_Y1_ORDER_W<28> {
256 REG_Y1_ORDER_W::new(self)
257 }
258 #[doc = "Bits 30:31"]
259 #[inline(always)]
260 #[must_use]
261 pub fn reg_v0_order(&mut self) -> REG_V0_ORDER_W<30> {
262 REG_V0_ORDER_W::new(self)
263 }
264 #[doc = "Writes raw bits to the register."]
265 #[inline(always)]
266 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
267 self.0.bits(bits);
268 self
269 }
270}
271#[doc = "mjpeg_control_1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mjpeg_control_1](index.html) module"]
272pub struct MJPEG_CONTROL_1_SPEC;
273impl crate::RegisterSpec for MJPEG_CONTROL_1_SPEC {
274 type Ux = u32;
275}
276#[doc = "`read()` method returns [mjpeg_control_1::R](R) reader structure"]
277impl crate::Readable for MJPEG_CONTROL_1_SPEC {
278 type Reader = R;
279}
280#[doc = "`write(|w| ..)` method takes [mjpeg_control_1::W](W) writer structure"]
281impl crate::Writable for MJPEG_CONTROL_1_SPEC {
282 type Writer = W;
283 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
284 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
285}
286#[doc = "`reset()` method sets mjpeg_control_1 to value 0"]
287impl crate::Resettable for MJPEG_CONTROL_1_SPEC {
288 const RESET_VALUE: Self::Ux = 0;
289}