1#[doc = "Register `irtx_pw` reader"]
2pub struct R(crate::R<IRTX_PW_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IRTX_PW_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IRTX_PW_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IRTX_PW_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `irtx_pw` writer"]
17pub struct W(crate::W<IRTX_PW_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IRTX_PW_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IRTX_PW_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IRTX_PW_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `cr_irtx_logic0_ph0_w` reader - "]
38pub type CR_IRTX_LOGIC0_PH0_W_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `cr_irtx_logic0_ph0_w` writer - "]
40pub type CR_IRTX_LOGIC0_PH0_W_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
42#[doc = "Field `cr_irtx_logic0_ph1_w` reader - "]
43pub type CR_IRTX_LOGIC0_PH1_W_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `cr_irtx_logic0_ph1_w` writer - "]
45pub type CR_IRTX_LOGIC0_PH1_W_W<'a, const O: u8> =
46 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
47#[doc = "Field `cr_irtx_logic1_ph0_w` reader - "]
48pub type CR_IRTX_LOGIC1_PH0_W_R = crate::FieldReader<u8, u8>;
49#[doc = "Field `cr_irtx_logic1_ph0_w` writer - "]
50pub type CR_IRTX_LOGIC1_PH0_W_W<'a, const O: u8> =
51 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
52#[doc = "Field `cr_irtx_logic1_ph1_w` reader - "]
53pub type CR_IRTX_LOGIC1_PH1_W_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `cr_irtx_logic1_ph1_w` writer - "]
55pub type CR_IRTX_LOGIC1_PH1_W_W<'a, const O: u8> =
56 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
57#[doc = "Field `cr_irtx_head_ph0_w` reader - "]
58pub type CR_IRTX_HEAD_PH0_W_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `cr_irtx_head_ph0_w` writer - "]
60pub type CR_IRTX_HEAD_PH0_W_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
62#[doc = "Field `cr_irtx_head_ph1_w` reader - "]
63pub type CR_IRTX_HEAD_PH1_W_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `cr_irtx_head_ph1_w` writer - "]
65pub type CR_IRTX_HEAD_PH1_W_W<'a, const O: u8> =
66 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
67#[doc = "Field `cr_irtx_tail_ph0_w` reader - "]
68pub type CR_IRTX_TAIL_PH0_W_R = crate::FieldReader<u8, u8>;
69#[doc = "Field `cr_irtx_tail_ph0_w` writer - "]
70pub type CR_IRTX_TAIL_PH0_W_W<'a, const O: u8> =
71 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
72#[doc = "Field `cr_irtx_tail_ph1_w` reader - "]
73pub type CR_IRTX_TAIL_PH1_W_R = crate::FieldReader<u8, u8>;
74#[doc = "Field `cr_irtx_tail_ph1_w` writer - "]
75pub type CR_IRTX_TAIL_PH1_W_W<'a, const O: u8> =
76 crate::FieldWriter<'a, u32, IRTX_PW_SPEC, u8, u8, 4, O>;
77impl R {
78 #[doc = "Bits 0:3"]
79 #[inline(always)]
80 pub fn cr_irtx_logic0_ph0_w(&self) -> CR_IRTX_LOGIC0_PH0_W_R {
81 CR_IRTX_LOGIC0_PH0_W_R::new((self.bits & 0x0f) as u8)
82 }
83 #[doc = "Bits 4:7"]
84 #[inline(always)]
85 pub fn cr_irtx_logic0_ph1_w(&self) -> CR_IRTX_LOGIC0_PH1_W_R {
86 CR_IRTX_LOGIC0_PH1_W_R::new(((self.bits >> 4) & 0x0f) as u8)
87 }
88 #[doc = "Bits 8:11"]
89 #[inline(always)]
90 pub fn cr_irtx_logic1_ph0_w(&self) -> CR_IRTX_LOGIC1_PH0_W_R {
91 CR_IRTX_LOGIC1_PH0_W_R::new(((self.bits >> 8) & 0x0f) as u8)
92 }
93 #[doc = "Bits 12:15"]
94 #[inline(always)]
95 pub fn cr_irtx_logic1_ph1_w(&self) -> CR_IRTX_LOGIC1_PH1_W_R {
96 CR_IRTX_LOGIC1_PH1_W_R::new(((self.bits >> 12) & 0x0f) as u8)
97 }
98 #[doc = "Bits 16:19"]
99 #[inline(always)]
100 pub fn cr_irtx_head_ph0_w(&self) -> CR_IRTX_HEAD_PH0_W_R {
101 CR_IRTX_HEAD_PH0_W_R::new(((self.bits >> 16) & 0x0f) as u8)
102 }
103 #[doc = "Bits 20:23"]
104 #[inline(always)]
105 pub fn cr_irtx_head_ph1_w(&self) -> CR_IRTX_HEAD_PH1_W_R {
106 CR_IRTX_HEAD_PH1_W_R::new(((self.bits >> 20) & 0x0f) as u8)
107 }
108 #[doc = "Bits 24:27"]
109 #[inline(always)]
110 pub fn cr_irtx_tail_ph0_w(&self) -> CR_IRTX_TAIL_PH0_W_R {
111 CR_IRTX_TAIL_PH0_W_R::new(((self.bits >> 24) & 0x0f) as u8)
112 }
113 #[doc = "Bits 28:31"]
114 #[inline(always)]
115 pub fn cr_irtx_tail_ph1_w(&self) -> CR_IRTX_TAIL_PH1_W_R {
116 CR_IRTX_TAIL_PH1_W_R::new(((self.bits >> 28) & 0x0f) as u8)
117 }
118}
119impl W {
120 #[doc = "Bits 0:3"]
121 #[inline(always)]
122 #[must_use]
123 pub fn cr_irtx_logic0_ph0_w(&mut self) -> CR_IRTX_LOGIC0_PH0_W_W<0> {
124 CR_IRTX_LOGIC0_PH0_W_W::new(self)
125 }
126 #[doc = "Bits 4:7"]
127 #[inline(always)]
128 #[must_use]
129 pub fn cr_irtx_logic0_ph1_w(&mut self) -> CR_IRTX_LOGIC0_PH1_W_W<4> {
130 CR_IRTX_LOGIC0_PH1_W_W::new(self)
131 }
132 #[doc = "Bits 8:11"]
133 #[inline(always)]
134 #[must_use]
135 pub fn cr_irtx_logic1_ph0_w(&mut self) -> CR_IRTX_LOGIC1_PH0_W_W<8> {
136 CR_IRTX_LOGIC1_PH0_W_W::new(self)
137 }
138 #[doc = "Bits 12:15"]
139 #[inline(always)]
140 #[must_use]
141 pub fn cr_irtx_logic1_ph1_w(&mut self) -> CR_IRTX_LOGIC1_PH1_W_W<12> {
142 CR_IRTX_LOGIC1_PH1_W_W::new(self)
143 }
144 #[doc = "Bits 16:19"]
145 #[inline(always)]
146 #[must_use]
147 pub fn cr_irtx_head_ph0_w(&mut self) -> CR_IRTX_HEAD_PH0_W_W<16> {
148 CR_IRTX_HEAD_PH0_W_W::new(self)
149 }
150 #[doc = "Bits 20:23"]
151 #[inline(always)]
152 #[must_use]
153 pub fn cr_irtx_head_ph1_w(&mut self) -> CR_IRTX_HEAD_PH1_W_W<20> {
154 CR_IRTX_HEAD_PH1_W_W::new(self)
155 }
156 #[doc = "Bits 24:27"]
157 #[inline(always)]
158 #[must_use]
159 pub fn cr_irtx_tail_ph0_w(&mut self) -> CR_IRTX_TAIL_PH0_W_W<24> {
160 CR_IRTX_TAIL_PH0_W_W::new(self)
161 }
162 #[doc = "Bits 28:31"]
163 #[inline(always)]
164 #[must_use]
165 pub fn cr_irtx_tail_ph1_w(&mut self) -> CR_IRTX_TAIL_PH1_W_W<28> {
166 CR_IRTX_TAIL_PH1_W_W::new(self)
167 }
168 #[doc = "Writes raw bits to the register."]
169 #[inline(always)]
170 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
171 self.0.bits(bits);
172 self
173 }
174}
175#[doc = "irtx_pw.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irtx_pw](index.html) module"]
176pub struct IRTX_PW_SPEC;
177impl crate::RegisterSpec for IRTX_PW_SPEC {
178 type Ux = u32;
179}
180#[doc = "`read()` method returns [irtx_pw::R](R) reader structure"]
181impl crate::Readable for IRTX_PW_SPEC {
182 type Reader = R;
183}
184#[doc = "`write(|w| ..)` method takes [irtx_pw::W](W) writer structure"]
185impl crate::Writable for IRTX_PW_SPEC {
186 type Writer = W;
187 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
188 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
189}
190#[doc = "`reset()` method sets irtx_pw to value 0"]
191impl crate::Resettable for IRTX_PW_SPEC {
192 const RESET_VALUE: Self::Ux = 0;
193}