bl702_pac/i2s/
i2s_fifo_config_0.rs

1#[doc = "Register `i2s_fifo_config_0` reader"]
2pub struct R(crate::R<I2S_FIFO_CONFIG_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<I2S_FIFO_CONFIG_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<I2S_FIFO_CONFIG_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<I2S_FIFO_CONFIG_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `i2s_fifo_config_0` writer"]
17pub struct W(crate::W<I2S_FIFO_CONFIG_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<I2S_FIFO_CONFIG_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<I2S_FIFO_CONFIG_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<I2S_FIFO_CONFIG_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `i2s_dma_tx_en` reader - "]
38pub type I2S_DMA_TX_EN_R = crate::BitReader<bool>;
39#[doc = "Field `i2s_dma_tx_en` writer - "]
40pub type I2S_DMA_TX_EN_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
42#[doc = "Field `i2s_dma_rx_en` reader - "]
43pub type I2S_DMA_RX_EN_R = crate::BitReader<bool>;
44#[doc = "Field `i2s_dma_rx_en` writer - "]
45pub type I2S_DMA_RX_EN_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
47#[doc = "Field `tx_fifo_clr` reader - "]
48pub type TX_FIFO_CLR_R = crate::BitReader<bool>;
49#[doc = "Field `tx_fifo_clr` writer - "]
50pub type TX_FIFO_CLR_W<'a, const O: u8> =
51    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
52#[doc = "Field `rx_fifo_clr` reader - "]
53pub type RX_FIFO_CLR_R = crate::BitReader<bool>;
54#[doc = "Field `rx_fifo_clr` writer - "]
55pub type RX_FIFO_CLR_W<'a, const O: u8> =
56    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
57#[doc = "Field `tx_fifo_overflow` reader - "]
58pub type TX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
59#[doc = "Field `tx_fifo_overflow` writer - "]
60pub type TX_FIFO_OVERFLOW_W<'a, const O: u8> =
61    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
62#[doc = "Field `tx_fifo_underflow` reader - "]
63pub type TX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
64#[doc = "Field `tx_fifo_underflow` writer - "]
65pub type TX_FIFO_UNDERFLOW_W<'a, const O: u8> =
66    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
67#[doc = "Field `rx_fifo_overflow` reader - "]
68pub type RX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
69#[doc = "Field `rx_fifo_overflow` writer - "]
70pub type RX_FIFO_OVERFLOW_W<'a, const O: u8> =
71    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
72#[doc = "Field `rx_fifo_underflow` reader - "]
73pub type RX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
74#[doc = "Field `rx_fifo_underflow` writer - "]
75pub type RX_FIFO_UNDERFLOW_W<'a, const O: u8> =
76    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
77#[doc = "Field `cr_fifo_lr_merge` reader - "]
78pub type CR_FIFO_LR_MERGE_R = crate::BitReader<bool>;
79#[doc = "Field `cr_fifo_lr_merge` writer - "]
80pub type CR_FIFO_LR_MERGE_W<'a, const O: u8> =
81    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
82#[doc = "Field `cr_fifo_lr_exchg` reader - "]
83pub type CR_FIFO_LR_EXCHG_R = crate::BitReader<bool>;
84#[doc = "Field `cr_fifo_lr_exchg` writer - "]
85pub type CR_FIFO_LR_EXCHG_W<'a, const O: u8> =
86    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
87#[doc = "Field `cr_fifo_24b_lj` reader - "]
88pub type CR_FIFO_24B_LJ_R = crate::BitReader<bool>;
89#[doc = "Field `cr_fifo_24b_lj` writer - "]
90pub type CR_FIFO_24B_LJ_W<'a, const O: u8> =
91    crate::BitWriter<'a, u32, I2S_FIFO_CONFIG_0_SPEC, bool, O>;
92impl R {
93    #[doc = "Bit 0"]
94    #[inline(always)]
95    pub fn i2s_dma_tx_en(&self) -> I2S_DMA_TX_EN_R {
96        I2S_DMA_TX_EN_R::new((self.bits & 1) != 0)
97    }
98    #[doc = "Bit 1"]
99    #[inline(always)]
100    pub fn i2s_dma_rx_en(&self) -> I2S_DMA_RX_EN_R {
101        I2S_DMA_RX_EN_R::new(((self.bits >> 1) & 1) != 0)
102    }
103    #[doc = "Bit 2"]
104    #[inline(always)]
105    pub fn tx_fifo_clr(&self) -> TX_FIFO_CLR_R {
106        TX_FIFO_CLR_R::new(((self.bits >> 2) & 1) != 0)
107    }
108    #[doc = "Bit 3"]
109    #[inline(always)]
110    pub fn rx_fifo_clr(&self) -> RX_FIFO_CLR_R {
111        RX_FIFO_CLR_R::new(((self.bits >> 3) & 1) != 0)
112    }
113    #[doc = "Bit 4"]
114    #[inline(always)]
115    pub fn tx_fifo_overflow(&self) -> TX_FIFO_OVERFLOW_R {
116        TX_FIFO_OVERFLOW_R::new(((self.bits >> 4) & 1) != 0)
117    }
118    #[doc = "Bit 5"]
119    #[inline(always)]
120    pub fn tx_fifo_underflow(&self) -> TX_FIFO_UNDERFLOW_R {
121        TX_FIFO_UNDERFLOW_R::new(((self.bits >> 5) & 1) != 0)
122    }
123    #[doc = "Bit 6"]
124    #[inline(always)]
125    pub fn rx_fifo_overflow(&self) -> RX_FIFO_OVERFLOW_R {
126        RX_FIFO_OVERFLOW_R::new(((self.bits >> 6) & 1) != 0)
127    }
128    #[doc = "Bit 7"]
129    #[inline(always)]
130    pub fn rx_fifo_underflow(&self) -> RX_FIFO_UNDERFLOW_R {
131        RX_FIFO_UNDERFLOW_R::new(((self.bits >> 7) & 1) != 0)
132    }
133    #[doc = "Bit 8"]
134    #[inline(always)]
135    pub fn cr_fifo_lr_merge(&self) -> CR_FIFO_LR_MERGE_R {
136        CR_FIFO_LR_MERGE_R::new(((self.bits >> 8) & 1) != 0)
137    }
138    #[doc = "Bit 9"]
139    #[inline(always)]
140    pub fn cr_fifo_lr_exchg(&self) -> CR_FIFO_LR_EXCHG_R {
141        CR_FIFO_LR_EXCHG_R::new(((self.bits >> 9) & 1) != 0)
142    }
143    #[doc = "Bit 10"]
144    #[inline(always)]
145    pub fn cr_fifo_24b_lj(&self) -> CR_FIFO_24B_LJ_R {
146        CR_FIFO_24B_LJ_R::new(((self.bits >> 10) & 1) != 0)
147    }
148}
149impl W {
150    #[doc = "Bit 0"]
151    #[inline(always)]
152    #[must_use]
153    pub fn i2s_dma_tx_en(&mut self) -> I2S_DMA_TX_EN_W<0> {
154        I2S_DMA_TX_EN_W::new(self)
155    }
156    #[doc = "Bit 1"]
157    #[inline(always)]
158    #[must_use]
159    pub fn i2s_dma_rx_en(&mut self) -> I2S_DMA_RX_EN_W<1> {
160        I2S_DMA_RX_EN_W::new(self)
161    }
162    #[doc = "Bit 2"]
163    #[inline(always)]
164    #[must_use]
165    pub fn tx_fifo_clr(&mut self) -> TX_FIFO_CLR_W<2> {
166        TX_FIFO_CLR_W::new(self)
167    }
168    #[doc = "Bit 3"]
169    #[inline(always)]
170    #[must_use]
171    pub fn rx_fifo_clr(&mut self) -> RX_FIFO_CLR_W<3> {
172        RX_FIFO_CLR_W::new(self)
173    }
174    #[doc = "Bit 4"]
175    #[inline(always)]
176    #[must_use]
177    pub fn tx_fifo_overflow(&mut self) -> TX_FIFO_OVERFLOW_W<4> {
178        TX_FIFO_OVERFLOW_W::new(self)
179    }
180    #[doc = "Bit 5"]
181    #[inline(always)]
182    #[must_use]
183    pub fn tx_fifo_underflow(&mut self) -> TX_FIFO_UNDERFLOW_W<5> {
184        TX_FIFO_UNDERFLOW_W::new(self)
185    }
186    #[doc = "Bit 6"]
187    #[inline(always)]
188    #[must_use]
189    pub fn rx_fifo_overflow(&mut self) -> RX_FIFO_OVERFLOW_W<6> {
190        RX_FIFO_OVERFLOW_W::new(self)
191    }
192    #[doc = "Bit 7"]
193    #[inline(always)]
194    #[must_use]
195    pub fn rx_fifo_underflow(&mut self) -> RX_FIFO_UNDERFLOW_W<7> {
196        RX_FIFO_UNDERFLOW_W::new(self)
197    }
198    #[doc = "Bit 8"]
199    #[inline(always)]
200    #[must_use]
201    pub fn cr_fifo_lr_merge(&mut self) -> CR_FIFO_LR_MERGE_W<8> {
202        CR_FIFO_LR_MERGE_W::new(self)
203    }
204    #[doc = "Bit 9"]
205    #[inline(always)]
206    #[must_use]
207    pub fn cr_fifo_lr_exchg(&mut self) -> CR_FIFO_LR_EXCHG_W<9> {
208        CR_FIFO_LR_EXCHG_W::new(self)
209    }
210    #[doc = "Bit 10"]
211    #[inline(always)]
212    #[must_use]
213    pub fn cr_fifo_24b_lj(&mut self) -> CR_FIFO_24B_LJ_W<10> {
214        CR_FIFO_24B_LJ_W::new(self)
215    }
216    #[doc = "Writes raw bits to the register."]
217    #[inline(always)]
218    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
219        self.0.bits(bits);
220        self
221    }
222}
223#[doc = "i2s_fifo_config_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [i2s_fifo_config_0](index.html) module"]
224pub struct I2S_FIFO_CONFIG_0_SPEC;
225impl crate::RegisterSpec for I2S_FIFO_CONFIG_0_SPEC {
226    type Ux = u32;
227}
228#[doc = "`read()` method returns [i2s_fifo_config_0::R](R) reader structure"]
229impl crate::Readable for I2S_FIFO_CONFIG_0_SPEC {
230    type Reader = R;
231}
232#[doc = "`write(|w| ..)` method takes [i2s_fifo_config_0::W](W) writer structure"]
233impl crate::Writable for I2S_FIFO_CONFIG_0_SPEC {
234    type Writer = W;
235    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
236    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
237}
238#[doc = "`reset()` method sets i2s_fifo_config_0 to value 0"]
239impl crate::Resettable for I2S_FIFO_CONFIG_0_SPEC {
240    const RESET_VALUE: Self::Ux = 0;
241}
bl702_pac/i2s/i2s_fifo_config_0.rs

bl702_pac/i2s/
i2s_fifo_config_0.rs
