1#[doc = "Register `HBN_CTL` reader"]
2pub struct R(crate::R<HBN_CTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HBN_CTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HBN_CTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HBN_CTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HBN_CTL` writer"]
17pub struct W(crate::W<HBN_CTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HBN_CTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HBN_CTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HBN_CTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `rtc_ctl` reader - "]
38pub type RTC_CTL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `rtc_ctl` writer - "]
40pub type RTC_CTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HBN_CTL_SPEC, u8, u8, 7, O>;
41#[doc = "Field `hbn_mode` reader - "]
42pub type HBN_MODE_R = crate::BitReader<bool>;
43#[doc = "Field `hbn_mode` writer - "]
44pub type HBN_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
45#[doc = "Field `trap_mode` reader - "]
46pub type TRAP_MODE_R = crate::BitReader<bool>;
47#[doc = "Field `trap_mode` writer - "]
48pub type TRAP_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
49#[doc = "Field `pwrdn_hbn_core` reader - "]
50pub type PWRDN_HBN_CORE_R = crate::BitReader<bool>;
51#[doc = "Field `pwrdn_hbn_core` writer - "]
52pub type PWRDN_HBN_CORE_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
53#[doc = "Field `pwrdn_hbn_rtc` reader - "]
54pub type PWRDN_HBN_RTC_R = crate::BitReader<bool>;
55#[doc = "Field `pwrdn_hbn_rtc` writer - "]
56pub type PWRDN_HBN_RTC_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
57#[doc = "Field `sw_rst` reader - "]
58pub type SW_RST_R = crate::BitReader<bool>;
59#[doc = "Field `sw_rst` writer - "]
60pub type SW_RST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
61#[doc = "Field `hbn_dis_pwr_off_ldo11` reader - "]
62pub type HBN_DIS_PWR_OFF_LDO11_R = crate::BitReader<bool>;
63#[doc = "Field `hbn_dis_pwr_off_ldo11` writer - "]
64pub type HBN_DIS_PWR_OFF_LDO11_W<'a, const O: u8> =
65 crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
66#[doc = "Field `hbn_dis_pwr_off_ldo11_rt` reader - "]
67pub type HBN_DIS_PWR_OFF_LDO11_RT_R = crate::BitReader<bool>;
68#[doc = "Field `hbn_dis_pwr_off_ldo11_rt` writer - "]
69pub type HBN_DIS_PWR_OFF_LDO11_RT_W<'a, const O: u8> =
70 crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
71#[doc = "Field `hbn_ldo11_rt_vout_sel` reader - "]
72pub type HBN_LDO11_RT_VOUT_SEL_R = crate::FieldReader<u8, u8>;
73#[doc = "Field `hbn_ldo11_rt_vout_sel` writer - "]
74pub type HBN_LDO11_RT_VOUT_SEL_W<'a, const O: u8> =
75 crate::FieldWriter<'a, u32, HBN_CTL_SPEC, u8, u8, 4, O>;
76#[doc = "Field `hbn_ldo11_aon_vout_sel` reader - "]
77pub type HBN_LDO11_AON_VOUT_SEL_R = crate::FieldReader<u8, u8>;
78#[doc = "Field `hbn_ldo11_aon_vout_sel` writer - "]
79pub type HBN_LDO11_AON_VOUT_SEL_W<'a, const O: u8> =
80 crate::FieldWriter<'a, u32, HBN_CTL_SPEC, u8, u8, 4, O>;
81#[doc = "Field `pu_dcdc18_aon` reader - "]
82pub type PU_DCDC18_AON_R = crate::BitReader<bool>;
83#[doc = "Field `pu_dcdc18_aon` writer - "]
84pub type PU_DCDC18_AON_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
85#[doc = "Field `rtc_dly_option` reader - "]
86pub type RTC_DLY_OPTION_R = crate::BitReader<bool>;
87#[doc = "Field `rtc_dly_option` writer - "]
88pub type RTC_DLY_OPTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
89#[doc = "Field `pwr_on_option` reader - "]
90pub type PWR_ON_OPTION_R = crate::BitReader<bool>;
91#[doc = "Field `pwr_on_option` writer - "]
92pub type PWR_ON_OPTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
93#[doc = "Field `sram_slp_option` reader - "]
94pub type SRAM_SLP_OPTION_R = crate::BitReader<bool>;
95#[doc = "Field `sram_slp_option` writer - "]
96pub type SRAM_SLP_OPTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
97#[doc = "Field `sram_slp` reader - "]
98pub type SRAM_SLP_R = crate::BitReader<bool>;
99#[doc = "Field `sram_slp` writer - "]
100pub type SRAM_SLP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HBN_CTL_SPEC, bool, O>;
101#[doc = "Field `hbn_state` reader - "]
102pub type HBN_STATE_R = crate::FieldReader<u8, u8>;
103#[doc = "Field `hbn_state` writer - "]
104pub type HBN_STATE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HBN_CTL_SPEC, u8, u8, 4, O>;
105impl R {
106 #[doc = "Bits 0:6"]
107 #[inline(always)]
108 pub fn rtc_ctl(&self) -> RTC_CTL_R {
109 RTC_CTL_R::new((self.bits & 0x7f) as u8)
110 }
111 #[doc = "Bit 7"]
112 #[inline(always)]
113 pub fn hbn_mode(&self) -> HBN_MODE_R {
114 HBN_MODE_R::new(((self.bits >> 7) & 1) != 0)
115 }
116 #[doc = "Bit 8"]
117 #[inline(always)]
118 pub fn trap_mode(&self) -> TRAP_MODE_R {
119 TRAP_MODE_R::new(((self.bits >> 8) & 1) != 0)
120 }
121 #[doc = "Bit 9"]
122 #[inline(always)]
123 pub fn pwrdn_hbn_core(&self) -> PWRDN_HBN_CORE_R {
124 PWRDN_HBN_CORE_R::new(((self.bits >> 9) & 1) != 0)
125 }
126 #[doc = "Bit 11"]
127 #[inline(always)]
128 pub fn pwrdn_hbn_rtc(&self) -> PWRDN_HBN_RTC_R {
129 PWRDN_HBN_RTC_R::new(((self.bits >> 11) & 1) != 0)
130 }
131 #[doc = "Bit 12"]
132 #[inline(always)]
133 pub fn sw_rst(&self) -> SW_RST_R {
134 SW_RST_R::new(((self.bits >> 12) & 1) != 0)
135 }
136 #[doc = "Bit 13"]
137 #[inline(always)]
138 pub fn hbn_dis_pwr_off_ldo11(&self) -> HBN_DIS_PWR_OFF_LDO11_R {
139 HBN_DIS_PWR_OFF_LDO11_R::new(((self.bits >> 13) & 1) != 0)
140 }
141 #[doc = "Bit 14"]
142 #[inline(always)]
143 pub fn hbn_dis_pwr_off_ldo11_rt(&self) -> HBN_DIS_PWR_OFF_LDO11_RT_R {
144 HBN_DIS_PWR_OFF_LDO11_RT_R::new(((self.bits >> 14) & 1) != 0)
145 }
146 #[doc = "Bits 15:18"]
147 #[inline(always)]
148 pub fn hbn_ldo11_rt_vout_sel(&self) -> HBN_LDO11_RT_VOUT_SEL_R {
149 HBN_LDO11_RT_VOUT_SEL_R::new(((self.bits >> 15) & 0x0f) as u8)
150 }
151 #[doc = "Bits 19:22"]
152 #[inline(always)]
153 pub fn hbn_ldo11_aon_vout_sel(&self) -> HBN_LDO11_AON_VOUT_SEL_R {
154 HBN_LDO11_AON_VOUT_SEL_R::new(((self.bits >> 19) & 0x0f) as u8)
155 }
156 #[doc = "Bit 23"]
157 #[inline(always)]
158 pub fn pu_dcdc18_aon(&self) -> PU_DCDC18_AON_R {
159 PU_DCDC18_AON_R::new(((self.bits >> 23) & 1) != 0)
160 }
161 #[doc = "Bit 24"]
162 #[inline(always)]
163 pub fn rtc_dly_option(&self) -> RTC_DLY_OPTION_R {
164 RTC_DLY_OPTION_R::new(((self.bits >> 24) & 1) != 0)
165 }
166 #[doc = "Bit 25"]
167 #[inline(always)]
168 pub fn pwr_on_option(&self) -> PWR_ON_OPTION_R {
169 PWR_ON_OPTION_R::new(((self.bits >> 25) & 1) != 0)
170 }
171 #[doc = "Bit 26"]
172 #[inline(always)]
173 pub fn sram_slp_option(&self) -> SRAM_SLP_OPTION_R {
174 SRAM_SLP_OPTION_R::new(((self.bits >> 26) & 1) != 0)
175 }
176 #[doc = "Bit 27"]
177 #[inline(always)]
178 pub fn sram_slp(&self) -> SRAM_SLP_R {
179 SRAM_SLP_R::new(((self.bits >> 27) & 1) != 0)
180 }
181 #[doc = "Bits 28:31"]
182 #[inline(always)]
183 pub fn hbn_state(&self) -> HBN_STATE_R {
184 HBN_STATE_R::new(((self.bits >> 28) & 0x0f) as u8)
185 }
186}
187impl W {
188 #[doc = "Bits 0:6"]
189 #[inline(always)]
190 #[must_use]
191 pub fn rtc_ctl(&mut self) -> RTC_CTL_W<0> {
192 RTC_CTL_W::new(self)
193 }
194 #[doc = "Bit 7"]
195 #[inline(always)]
196 #[must_use]
197 pub fn hbn_mode(&mut self) -> HBN_MODE_W<7> {
198 HBN_MODE_W::new(self)
199 }
200 #[doc = "Bit 8"]
201 #[inline(always)]
202 #[must_use]
203 pub fn trap_mode(&mut self) -> TRAP_MODE_W<8> {
204 TRAP_MODE_W::new(self)
205 }
206 #[doc = "Bit 9"]
207 #[inline(always)]
208 #[must_use]
209 pub fn pwrdn_hbn_core(&mut self) -> PWRDN_HBN_CORE_W<9> {
210 PWRDN_HBN_CORE_W::new(self)
211 }
212 #[doc = "Bit 11"]
213 #[inline(always)]
214 #[must_use]
215 pub fn pwrdn_hbn_rtc(&mut self) -> PWRDN_HBN_RTC_W<11> {
216 PWRDN_HBN_RTC_W::new(self)
217 }
218 #[doc = "Bit 12"]
219 #[inline(always)]
220 #[must_use]
221 pub fn sw_rst(&mut self) -> SW_RST_W<12> {
222 SW_RST_W::new(self)
223 }
224 #[doc = "Bit 13"]
225 #[inline(always)]
226 #[must_use]
227 pub fn hbn_dis_pwr_off_ldo11(&mut self) -> HBN_DIS_PWR_OFF_LDO11_W<13> {
228 HBN_DIS_PWR_OFF_LDO11_W::new(self)
229 }
230 #[doc = "Bit 14"]
231 #[inline(always)]
232 #[must_use]
233 pub fn hbn_dis_pwr_off_ldo11_rt(&mut self) -> HBN_DIS_PWR_OFF_LDO11_RT_W<14> {
234 HBN_DIS_PWR_OFF_LDO11_RT_W::new(self)
235 }
236 #[doc = "Bits 15:18"]
237 #[inline(always)]
238 #[must_use]
239 pub fn hbn_ldo11_rt_vout_sel(&mut self) -> HBN_LDO11_RT_VOUT_SEL_W<15> {
240 HBN_LDO11_RT_VOUT_SEL_W::new(self)
241 }
242 #[doc = "Bits 19:22"]
243 #[inline(always)]
244 #[must_use]
245 pub fn hbn_ldo11_aon_vout_sel(&mut self) -> HBN_LDO11_AON_VOUT_SEL_W<19> {
246 HBN_LDO11_AON_VOUT_SEL_W::new(self)
247 }
248 #[doc = "Bit 23"]
249 #[inline(always)]
250 #[must_use]
251 pub fn pu_dcdc18_aon(&mut self) -> PU_DCDC18_AON_W<23> {
252 PU_DCDC18_AON_W::new(self)
253 }
254 #[doc = "Bit 24"]
255 #[inline(always)]
256 #[must_use]
257 pub fn rtc_dly_option(&mut self) -> RTC_DLY_OPTION_W<24> {
258 RTC_DLY_OPTION_W::new(self)
259 }
260 #[doc = "Bit 25"]
261 #[inline(always)]
262 #[must_use]
263 pub fn pwr_on_option(&mut self) -> PWR_ON_OPTION_W<25> {
264 PWR_ON_OPTION_W::new(self)
265 }
266 #[doc = "Bit 26"]
267 #[inline(always)]
268 #[must_use]
269 pub fn sram_slp_option(&mut self) -> SRAM_SLP_OPTION_W<26> {
270 SRAM_SLP_OPTION_W::new(self)
271 }
272 #[doc = "Bit 27"]
273 #[inline(always)]
274 #[must_use]
275 pub fn sram_slp(&mut self) -> SRAM_SLP_W<27> {
276 SRAM_SLP_W::new(self)
277 }
278 #[doc = "Bits 28:31"]
279 #[inline(always)]
280 #[must_use]
281 pub fn hbn_state(&mut self) -> HBN_STATE_W<28> {
282 HBN_STATE_W::new(self)
283 }
284 #[doc = "Writes raw bits to the register."]
285 #[inline(always)]
286 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
287 self.0.bits(bits);
288 self
289 }
290}
291#[doc = "HBN_CTL.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hbn_ctl](index.html) module"]
292pub struct HBN_CTL_SPEC;
293impl crate::RegisterSpec for HBN_CTL_SPEC {
294 type Ux = u32;
295}
296#[doc = "`read()` method returns [hbn_ctl::R](R) reader structure"]
297impl crate::Readable for HBN_CTL_SPEC {
298 type Reader = R;
299}
300#[doc = "`write(|w| ..)` method takes [hbn_ctl::W](W) writer structure"]
301impl crate::Writable for HBN_CTL_SPEC {
302 type Writer = W;
303 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
304 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
305}
306#[doc = "`reset()` method sets HBN_CTL to value 0"]
307impl crate::Resettable for HBN_CTL_SPEC {
308 const RESET_VALUE: Self::Ux = 0;
309}