bl702_pac/glb/
pdm_clk_ctrl.rs

1#[doc = "Register `PDM_CLK_CTRL` reader"]
2pub struct R(crate::R<PDM_CLK_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PDM_CLK_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PDM_CLK_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PDM_CLK_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PDM_CLK_CTRL` writer"]
17pub struct W(crate::W<PDM_CLK_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PDM_CLK_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PDM_CLK_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PDM_CLK_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `reg_pdm0_clk_div` reader - "]
38pub type REG_PDM0_CLK_DIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `reg_pdm0_clk_div` writer - "]
40pub type REG_PDM0_CLK_DIV_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, PDM_CLK_CTRL_SPEC, u8, u8, 6, O>;
42#[doc = "Field `reg_pdm0_clk_en` reader - "]
43pub type REG_PDM0_CLK_EN_R = crate::BitReader<bool>;
44#[doc = "Field `reg_pdm0_clk_en` writer - "]
45pub type REG_PDM0_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PDM_CLK_CTRL_SPEC, bool, O>;
46impl R {
47    #[doc = "Bits 0:5"]
48    #[inline(always)]
49    pub fn reg_pdm0_clk_div(&self) -> REG_PDM0_CLK_DIV_R {
50        REG_PDM0_CLK_DIV_R::new((self.bits & 0x3f) as u8)
51    }
52    #[doc = "Bit 7"]
53    #[inline(always)]
54    pub fn reg_pdm0_clk_en(&self) -> REG_PDM0_CLK_EN_R {
55        REG_PDM0_CLK_EN_R::new(((self.bits >> 7) & 1) != 0)
56    }
57}
58impl W {
59    #[doc = "Bits 0:5"]
60    #[inline(always)]
61    #[must_use]
62    pub fn reg_pdm0_clk_div(&mut self) -> REG_PDM0_CLK_DIV_W<0> {
63        REG_PDM0_CLK_DIV_W::new(self)
64    }
65    #[doc = "Bit 7"]
66    #[inline(always)]
67    #[must_use]
68    pub fn reg_pdm0_clk_en(&mut self) -> REG_PDM0_CLK_EN_W<7> {
69        REG_PDM0_CLK_EN_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "PDM_CLK_CTRL.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdm_clk_ctrl](index.html) module"]
79pub struct PDM_CLK_CTRL_SPEC;
80impl crate::RegisterSpec for PDM_CLK_CTRL_SPEC {
81    type Ux = u32;
82}
83#[doc = "`read()` method returns [pdm_clk_ctrl::R](R) reader structure"]
84impl crate::Readable for PDM_CLK_CTRL_SPEC {
85    type Reader = R;
86}
87#[doc = "`write(|w| ..)` method takes [pdm_clk_ctrl::W](W) writer structure"]
88impl crate::Writable for PDM_CLK_CTRL_SPEC {
89    type Writer = W;
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
92}
93#[doc = "`reset()` method sets PDM_CLK_CTRL to value 0"]
94impl crate::Resettable for PDM_CLK_CTRL_SPEC {
95    const RESET_VALUE: Self::Ux = 0;
96}
bl702_pac/glb/pdm_clk_ctrl.rs

bl702_pac/glb/
pdm_clk_ctrl.rs
