bl702_pac/glb/
mbist_ctl.rs

1#[doc = "Register `MBIST_CTL` reader"]
2pub struct R(crate::R<MBIST_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MBIST_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MBIST_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MBIST_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MBIST_CTL` writer"]
17pub struct W(crate::W<MBIST_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MBIST_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MBIST_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MBIST_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `irom_mbist_mode` reader - "]
38pub type IROM_MBIST_MODE_R = crate::BitReader<bool>;
39#[doc = "Field `irom_mbist_mode` writer - "]
40pub type IROM_MBIST_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MBIST_CTL_SPEC, bool, O>;
41#[doc = "Field `hsram_mem_mbist_mode` reader - "]
42pub type HSRAM_MEM_MBIST_MODE_R = crate::BitReader<bool>;
43#[doc = "Field `hsram_mem_mbist_mode` writer - "]
44pub type HSRAM_MEM_MBIST_MODE_W<'a, const O: u8> =
45    crate::BitWriter<'a, u32, MBIST_CTL_SPEC, bool, O>;
46#[doc = "Field `hsram_cache_mbist_mode` reader - "]
47pub type HSRAM_CACHE_MBIST_MODE_R = crate::BitReader<bool>;
48#[doc = "Field `hsram_cache_mbist_mode` writer - "]
49pub type HSRAM_CACHE_MBIST_MODE_W<'a, const O: u8> =
50    crate::BitWriter<'a, u32, MBIST_CTL_SPEC, bool, O>;
51#[doc = "Field `tag_mbist_mode` reader - "]
52pub type TAG_MBIST_MODE_R = crate::BitReader<bool>;
53#[doc = "Field `tag_mbist_mode` writer - "]
54pub type TAG_MBIST_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MBIST_CTL_SPEC, bool, O>;
55#[doc = "Field `ocram_mbist_mode` reader - "]
56pub type OCRAM_MBIST_MODE_R = crate::BitReader<bool>;
57#[doc = "Field `ocram_mbist_mode` writer - "]
58pub type OCRAM_MBIST_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MBIST_CTL_SPEC, bool, O>;
59#[doc = "Field `em_ram_mbist_mode` reader - "]
60pub type EM_RAM_MBIST_MODE_R = crate::BitReader<bool>;
61#[doc = "Field `em_ram_mbist_mode` writer - "]
62pub type EM_RAM_MBIST_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MBIST_CTL_SPEC, bool, O>;
63#[doc = "Field `reg_mbist_rst_n` reader - "]
64pub type REG_MBIST_RST_N_R = crate::BitReader<bool>;
65#[doc = "Field `reg_mbist_rst_n` writer - "]
66pub type REG_MBIST_RST_N_W<'a, const O: u8> = crate::BitWriter<'a, u32, MBIST_CTL_SPEC, bool, O>;
67impl R {
68    #[doc = "Bit 0"]
69    #[inline(always)]
70    pub fn irom_mbist_mode(&self) -> IROM_MBIST_MODE_R {
71        IROM_MBIST_MODE_R::new((self.bits & 1) != 0)
72    }
73    #[doc = "Bit 1"]
74    #[inline(always)]
75    pub fn hsram_mem_mbist_mode(&self) -> HSRAM_MEM_MBIST_MODE_R {
76        HSRAM_MEM_MBIST_MODE_R::new(((self.bits >> 1) & 1) != 0)
77    }
78    #[doc = "Bit 2"]
79    #[inline(always)]
80    pub fn hsram_cache_mbist_mode(&self) -> HSRAM_CACHE_MBIST_MODE_R {
81        HSRAM_CACHE_MBIST_MODE_R::new(((self.bits >> 2) & 1) != 0)
82    }
83    #[doc = "Bit 3"]
84    #[inline(always)]
85    pub fn tag_mbist_mode(&self) -> TAG_MBIST_MODE_R {
86        TAG_MBIST_MODE_R::new(((self.bits >> 3) & 1) != 0)
87    }
88    #[doc = "Bit 4"]
89    #[inline(always)]
90    pub fn ocram_mbist_mode(&self) -> OCRAM_MBIST_MODE_R {
91        OCRAM_MBIST_MODE_R::new(((self.bits >> 4) & 1) != 0)
92    }
93    #[doc = "Bit 5"]
94    #[inline(always)]
95    pub fn em_ram_mbist_mode(&self) -> EM_RAM_MBIST_MODE_R {
96        EM_RAM_MBIST_MODE_R::new(((self.bits >> 5) & 1) != 0)
97    }
98    #[doc = "Bit 31"]
99    #[inline(always)]
100    pub fn reg_mbist_rst_n(&self) -> REG_MBIST_RST_N_R {
101        REG_MBIST_RST_N_R::new(((self.bits >> 31) & 1) != 0)
102    }
103}
104impl W {
105    #[doc = "Bit 0"]
106    #[inline(always)]
107    #[must_use]
108    pub fn irom_mbist_mode(&mut self) -> IROM_MBIST_MODE_W<0> {
109        IROM_MBIST_MODE_W::new(self)
110    }
111    #[doc = "Bit 1"]
112    #[inline(always)]
113    #[must_use]
114    pub fn hsram_mem_mbist_mode(&mut self) -> HSRAM_MEM_MBIST_MODE_W<1> {
115        HSRAM_MEM_MBIST_MODE_W::new(self)
116    }
117    #[doc = "Bit 2"]
118    #[inline(always)]
119    #[must_use]
120    pub fn hsram_cache_mbist_mode(&mut self) -> HSRAM_CACHE_MBIST_MODE_W<2> {
121        HSRAM_CACHE_MBIST_MODE_W::new(self)
122    }
123    #[doc = "Bit 3"]
124    #[inline(always)]
125    #[must_use]
126    pub fn tag_mbist_mode(&mut self) -> TAG_MBIST_MODE_W<3> {
127        TAG_MBIST_MODE_W::new(self)
128    }
129    #[doc = "Bit 4"]
130    #[inline(always)]
131    #[must_use]
132    pub fn ocram_mbist_mode(&mut self) -> OCRAM_MBIST_MODE_W<4> {
133        OCRAM_MBIST_MODE_W::new(self)
134    }
135    #[doc = "Bit 5"]
136    #[inline(always)]
137    #[must_use]
138    pub fn em_ram_mbist_mode(&mut self) -> EM_RAM_MBIST_MODE_W<5> {
139        EM_RAM_MBIST_MODE_W::new(self)
140    }
141    #[doc = "Bit 31"]
142    #[inline(always)]
143    #[must_use]
144    pub fn reg_mbist_rst_n(&mut self) -> REG_MBIST_RST_N_W<31> {
145        REG_MBIST_RST_N_W::new(self)
146    }
147    #[doc = "Writes raw bits to the register."]
148    #[inline(always)]
149    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
150        self.0.bits(bits);
151        self
152    }
153}
154#[doc = "MBIST_CTL.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mbist_ctl](index.html) module"]
155pub struct MBIST_CTL_SPEC;
156impl crate::RegisterSpec for MBIST_CTL_SPEC {
157    type Ux = u32;
158}
159#[doc = "`read()` method returns [mbist_ctl::R](R) reader structure"]
160impl crate::Readable for MBIST_CTL_SPEC {
161    type Reader = R;
162}
163#[doc = "`write(|w| ..)` method takes [mbist_ctl::W](W) writer structure"]
164impl crate::Writable for MBIST_CTL_SPEC {
165    type Writer = W;
166    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
167    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
168}
169#[doc = "`reset()` method sets MBIST_CTL to value 0"]
170impl crate::Resettable for MBIST_CTL_SPEC {
171    const RESET_VALUE: Self::Ux = 0;
172}
bl702_pac/glb/mbist_ctl.rs

bl702_pac/glb/
mbist_ctl.rs
