bl702_pac/glb/
gpio_cfgctl9.rs

1#[doc = "Register `GPIO_CFGCTL9` reader"]
2pub struct R(crate::R<GPIO_CFGCTL9_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GPIO_CFGCTL9_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GPIO_CFGCTL9_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GPIO_CFGCTL9_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GPIO_CFGCTL9` writer"]
17pub struct W(crate::W<GPIO_CFGCTL9_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GPIO_CFGCTL9_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GPIO_CFGCTL9_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GPIO_CFGCTL9_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `reg_gpio_18_ie` reader - "]
38pub type REG_GPIO_18_IE_R = crate::BitReader<bool>;
39#[doc = "Field `reg_gpio_18_ie` writer - "]
40pub type REG_GPIO_18_IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
41#[doc = "Field `reg_gpio_18_smt` reader - "]
42pub type REG_GPIO_18_SMT_R = crate::BitReader<bool>;
43#[doc = "Field `reg_gpio_18_smt` writer - "]
44pub type REG_GPIO_18_SMT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
45#[doc = "Field `reg_gpio_18_drv` reader - "]
46pub type REG_GPIO_18_DRV_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `reg_gpio_18_drv` writer - "]
48pub type REG_GPIO_18_DRV_W<'a, const O: u8> =
49    crate::FieldWriter<'a, u32, GPIO_CFGCTL9_SPEC, u8, u8, 2, O>;
50#[doc = "Field `reg_gpio_18_pu` reader - "]
51pub type REG_GPIO_18_PU_R = crate::BitReader<bool>;
52#[doc = "Field `reg_gpio_18_pu` writer - "]
53pub type REG_GPIO_18_PU_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
54#[doc = "Field `reg_gpio_18_pd` reader - "]
55pub type REG_GPIO_18_PD_R = crate::BitReader<bool>;
56#[doc = "Field `reg_gpio_18_pd` writer - "]
57pub type REG_GPIO_18_PD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
58#[doc = "Field `reg_gpio_18_func_sel` reader - "]
59pub type REG_GPIO_18_FUNC_SEL_R = crate::FieldReader<u8, u8>;
60#[doc = "Field `reg_gpio_18_func_sel` writer - "]
61pub type REG_GPIO_18_FUNC_SEL_W<'a, const O: u8> =
62    crate::FieldWriter<'a, u32, GPIO_CFGCTL9_SPEC, u8, u8, 5, O>;
63#[doc = "Field `reg_gpio_19_ie` reader - "]
64pub type REG_GPIO_19_IE_R = crate::BitReader<bool>;
65#[doc = "Field `reg_gpio_19_ie` writer - "]
66pub type REG_GPIO_19_IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
67#[doc = "Field `reg_gpio_19_smt` reader - "]
68pub type REG_GPIO_19_SMT_R = crate::BitReader<bool>;
69#[doc = "Field `reg_gpio_19_smt` writer - "]
70pub type REG_GPIO_19_SMT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
71#[doc = "Field `reg_gpio_19_drv` reader - "]
72pub type REG_GPIO_19_DRV_R = crate::FieldReader<u8, u8>;
73#[doc = "Field `reg_gpio_19_drv` writer - "]
74pub type REG_GPIO_19_DRV_W<'a, const O: u8> =
75    crate::FieldWriter<'a, u32, GPIO_CFGCTL9_SPEC, u8, u8, 2, O>;
76#[doc = "Field `reg_gpio_19_pu` reader - "]
77pub type REG_GPIO_19_PU_R = crate::BitReader<bool>;
78#[doc = "Field `reg_gpio_19_pu` writer - "]
79pub type REG_GPIO_19_PU_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
80#[doc = "Field `reg_gpio_19_pd` reader - "]
81pub type REG_GPIO_19_PD_R = crate::BitReader<bool>;
82#[doc = "Field `reg_gpio_19_pd` writer - "]
83pub type REG_GPIO_19_PD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL9_SPEC, bool, O>;
84#[doc = "Field `reg_gpio_19_func_sel` reader - "]
85pub type REG_GPIO_19_FUNC_SEL_R = crate::FieldReader<u8, u8>;
86#[doc = "Field `reg_gpio_19_func_sel` writer - "]
87pub type REG_GPIO_19_FUNC_SEL_W<'a, const O: u8> =
88    crate::FieldWriter<'a, u32, GPIO_CFGCTL9_SPEC, u8, u8, 5, O>;
89impl R {
90    #[doc = "Bit 0"]
91    #[inline(always)]
92    pub fn reg_gpio_18_ie(&self) -> REG_GPIO_18_IE_R {
93        REG_GPIO_18_IE_R::new((self.bits & 1) != 0)
94    }
95    #[doc = "Bit 1"]
96    #[inline(always)]
97    pub fn reg_gpio_18_smt(&self) -> REG_GPIO_18_SMT_R {
98        REG_GPIO_18_SMT_R::new(((self.bits >> 1) & 1) != 0)
99    }
100    #[doc = "Bits 2:3"]
101    #[inline(always)]
102    pub fn reg_gpio_18_drv(&self) -> REG_GPIO_18_DRV_R {
103        REG_GPIO_18_DRV_R::new(((self.bits >> 2) & 3) as u8)
104    }
105    #[doc = "Bit 4"]
106    #[inline(always)]
107    pub fn reg_gpio_18_pu(&self) -> REG_GPIO_18_PU_R {
108        REG_GPIO_18_PU_R::new(((self.bits >> 4) & 1) != 0)
109    }
110    #[doc = "Bit 5"]
111    #[inline(always)]
112    pub fn reg_gpio_18_pd(&self) -> REG_GPIO_18_PD_R {
113        REG_GPIO_18_PD_R::new(((self.bits >> 5) & 1) != 0)
114    }
115    #[doc = "Bits 8:12"]
116    #[inline(always)]
117    pub fn reg_gpio_18_func_sel(&self) -> REG_GPIO_18_FUNC_SEL_R {
118        REG_GPIO_18_FUNC_SEL_R::new(((self.bits >> 8) & 0x1f) as u8)
119    }
120    #[doc = "Bit 16"]
121    #[inline(always)]
122    pub fn reg_gpio_19_ie(&self) -> REG_GPIO_19_IE_R {
123        REG_GPIO_19_IE_R::new(((self.bits >> 16) & 1) != 0)
124    }
125    #[doc = "Bit 17"]
126    #[inline(always)]
127    pub fn reg_gpio_19_smt(&self) -> REG_GPIO_19_SMT_R {
128        REG_GPIO_19_SMT_R::new(((self.bits >> 17) & 1) != 0)
129    }
130    #[doc = "Bits 18:19"]
131    #[inline(always)]
132    pub fn reg_gpio_19_drv(&self) -> REG_GPIO_19_DRV_R {
133        REG_GPIO_19_DRV_R::new(((self.bits >> 18) & 3) as u8)
134    }
135    #[doc = "Bit 20"]
136    #[inline(always)]
137    pub fn reg_gpio_19_pu(&self) -> REG_GPIO_19_PU_R {
138        REG_GPIO_19_PU_R::new(((self.bits >> 20) & 1) != 0)
139    }
140    #[doc = "Bit 21"]
141    #[inline(always)]
142    pub fn reg_gpio_19_pd(&self) -> REG_GPIO_19_PD_R {
143        REG_GPIO_19_PD_R::new(((self.bits >> 21) & 1) != 0)
144    }
145    #[doc = "Bits 24:28"]
146    #[inline(always)]
147    pub fn reg_gpio_19_func_sel(&self) -> REG_GPIO_19_FUNC_SEL_R {
148        REG_GPIO_19_FUNC_SEL_R::new(((self.bits >> 24) & 0x1f) as u8)
149    }
150}
151impl W {
152    #[doc = "Bit 0"]
153    #[inline(always)]
154    #[must_use]
155    pub fn reg_gpio_18_ie(&mut self) -> REG_GPIO_18_IE_W<0> {
156        REG_GPIO_18_IE_W::new(self)
157    }
158    #[doc = "Bit 1"]
159    #[inline(always)]
160    #[must_use]
161    pub fn reg_gpio_18_smt(&mut self) -> REG_GPIO_18_SMT_W<1> {
162        REG_GPIO_18_SMT_W::new(self)
163    }
164    #[doc = "Bits 2:3"]
165    #[inline(always)]
166    #[must_use]
167    pub fn reg_gpio_18_drv(&mut self) -> REG_GPIO_18_DRV_W<2> {
168        REG_GPIO_18_DRV_W::new(self)
169    }
170    #[doc = "Bit 4"]
171    #[inline(always)]
172    #[must_use]
173    pub fn reg_gpio_18_pu(&mut self) -> REG_GPIO_18_PU_W<4> {
174        REG_GPIO_18_PU_W::new(self)
175    }
176    #[doc = "Bit 5"]
177    #[inline(always)]
178    #[must_use]
179    pub fn reg_gpio_18_pd(&mut self) -> REG_GPIO_18_PD_W<5> {
180        REG_GPIO_18_PD_W::new(self)
181    }
182    #[doc = "Bits 8:12"]
183    #[inline(always)]
184    #[must_use]
185    pub fn reg_gpio_18_func_sel(&mut self) -> REG_GPIO_18_FUNC_SEL_W<8> {
186        REG_GPIO_18_FUNC_SEL_W::new(self)
187    }
188    #[doc = "Bit 16"]
189    #[inline(always)]
190    #[must_use]
191    pub fn reg_gpio_19_ie(&mut self) -> REG_GPIO_19_IE_W<16> {
192        REG_GPIO_19_IE_W::new(self)
193    }
194    #[doc = "Bit 17"]
195    #[inline(always)]
196    #[must_use]
197    pub fn reg_gpio_19_smt(&mut self) -> REG_GPIO_19_SMT_W<17> {
198        REG_GPIO_19_SMT_W::new(self)
199    }
200    #[doc = "Bits 18:19"]
201    #[inline(always)]
202    #[must_use]
203    pub fn reg_gpio_19_drv(&mut self) -> REG_GPIO_19_DRV_W<18> {
204        REG_GPIO_19_DRV_W::new(self)
205    }
206    #[doc = "Bit 20"]
207    #[inline(always)]
208    #[must_use]
209    pub fn reg_gpio_19_pu(&mut self) -> REG_GPIO_19_PU_W<20> {
210        REG_GPIO_19_PU_W::new(self)
211    }
212    #[doc = "Bit 21"]
213    #[inline(always)]
214    #[must_use]
215    pub fn reg_gpio_19_pd(&mut self) -> REG_GPIO_19_PD_W<21> {
216        REG_GPIO_19_PD_W::new(self)
217    }
218    #[doc = "Bits 24:28"]
219    #[inline(always)]
220    #[must_use]
221    pub fn reg_gpio_19_func_sel(&mut self) -> REG_GPIO_19_FUNC_SEL_W<24> {
222        REG_GPIO_19_FUNC_SEL_W::new(self)
223    }
224    #[doc = "Writes raw bits to the register."]
225    #[inline(always)]
226    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
227        self.0.bits(bits);
228        self
229    }
230}
231#[doc = "GPIO_CFGCTL9.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_cfgctl9](index.html) module"]
232pub struct GPIO_CFGCTL9_SPEC;
233impl crate::RegisterSpec for GPIO_CFGCTL9_SPEC {
234    type Ux = u32;
235}
236#[doc = "`read()` method returns [gpio_cfgctl9::R](R) reader structure"]
237impl crate::Readable for GPIO_CFGCTL9_SPEC {
238    type Reader = R;
239}
240#[doc = "`write(|w| ..)` method takes [gpio_cfgctl9::W](W) writer structure"]
241impl crate::Writable for GPIO_CFGCTL9_SPEC {
242    type Writer = W;
243    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
244    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
245}
246#[doc = "`reset()` method sets GPIO_CFGCTL9 to value 0"]
247impl crate::Resettable for GPIO_CFGCTL9_SPEC {
248    const RESET_VALUE: Self::Ux = 0;
249}
bl702_pac/glb/gpio_cfgctl9.rs

bl702_pac/glb/
gpio_cfgctl9.rs
