bl702_pac/glb/
gpio_cfgctl16.rs1#[doc = "Register `GPIO_CFGCTL16` reader"]
2pub struct R(crate::R<GPIO_CFGCTL16_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<GPIO_CFGCTL16_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<GPIO_CFGCTL16_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<GPIO_CFGCTL16_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `GPIO_CFGCTL16` writer"]
17pub struct W(crate::W<GPIO_CFGCTL16_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<GPIO_CFGCTL16_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<GPIO_CFGCTL16_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<GPIO_CFGCTL16_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `reg_gpio_32_ie` reader - "]
38pub type REG_GPIO_32_IE_R = crate::BitReader<bool>;
39#[doc = "Field `reg_gpio_32_ie` writer - "]
40pub type REG_GPIO_32_IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
41#[doc = "Field `reg_gpio_32_smt` reader - "]
42pub type REG_GPIO_32_SMT_R = crate::BitReader<bool>;
43#[doc = "Field `reg_gpio_32_smt` writer - "]
44pub type REG_GPIO_32_SMT_W<'a, const O: u8> =
45 crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
46#[doc = "Field `reg_gpio_32_drv` reader - "]
47pub type REG_GPIO_32_DRV_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `reg_gpio_32_drv` writer - "]
49pub type REG_GPIO_32_DRV_W<'a, const O: u8> =
50 crate::FieldWriter<'a, u32, GPIO_CFGCTL16_SPEC, u8, u8, 2, O>;
51#[doc = "Field `reg_gpio_32_pu` reader - "]
52pub type REG_GPIO_32_PU_R = crate::BitReader<bool>;
53#[doc = "Field `reg_gpio_32_pu` writer - "]
54pub type REG_GPIO_32_PU_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
55#[doc = "Field `reg_gpio_32_pd` reader - "]
56pub type REG_GPIO_32_PD_R = crate::BitReader<bool>;
57#[doc = "Field `reg_gpio_32_pd` writer - "]
58pub type REG_GPIO_32_PD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
59#[doc = "Field `reg_gpio_33_ie` reader - "]
60pub type REG_GPIO_33_IE_R = crate::BitReader<bool>;
61#[doc = "Field `reg_gpio_33_ie` writer - "]
62pub type REG_GPIO_33_IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
63#[doc = "Field `reg_gpio_33_smt` reader - "]
64pub type REG_GPIO_33_SMT_R = crate::BitReader<bool>;
65#[doc = "Field `reg_gpio_33_smt` writer - "]
66pub type REG_GPIO_33_SMT_W<'a, const O: u8> =
67 crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
68#[doc = "Field `reg_gpio_33_drv` reader - "]
69pub type REG_GPIO_33_DRV_R = crate::FieldReader<u8, u8>;
70#[doc = "Field `reg_gpio_33_drv` writer - "]
71pub type REG_GPIO_33_DRV_W<'a, const O: u8> =
72 crate::FieldWriter<'a, u32, GPIO_CFGCTL16_SPEC, u8, u8, 2, O>;
73#[doc = "Field `reg_gpio_33_pu` reader - "]
74pub type REG_GPIO_33_PU_R = crate::BitReader<bool>;
75#[doc = "Field `reg_gpio_33_pu` writer - "]
76pub type REG_GPIO_33_PU_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
77#[doc = "Field `reg_gpio_33_pd` reader - "]
78pub type REG_GPIO_33_PD_R = crate::BitReader<bool>;
79#[doc = "Field `reg_gpio_33_pd` writer - "]
80pub type REG_GPIO_33_PD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL16_SPEC, bool, O>;
81impl R {
82 #[doc = "Bit 0"]
83 #[inline(always)]
84 pub fn reg_gpio_32_ie(&self) -> REG_GPIO_32_IE_R {
85 REG_GPIO_32_IE_R::new((self.bits & 1) != 0)
86 }
87 #[doc = "Bit 1"]
88 #[inline(always)]
89 pub fn reg_gpio_32_smt(&self) -> REG_GPIO_32_SMT_R {
90 REG_GPIO_32_SMT_R::new(((self.bits >> 1) & 1) != 0)
91 }
92 #[doc = "Bits 2:3"]
93 #[inline(always)]
94 pub fn reg_gpio_32_drv(&self) -> REG_GPIO_32_DRV_R {
95 REG_GPIO_32_DRV_R::new(((self.bits >> 2) & 3) as u8)
96 }
97 #[doc = "Bit 4"]
98 #[inline(always)]
99 pub fn reg_gpio_32_pu(&self) -> REG_GPIO_32_PU_R {
100 REG_GPIO_32_PU_R::new(((self.bits >> 4) & 1) != 0)
101 }
102 #[doc = "Bit 5"]
103 #[inline(always)]
104 pub fn reg_gpio_32_pd(&self) -> REG_GPIO_32_PD_R {
105 REG_GPIO_32_PD_R::new(((self.bits >> 5) & 1) != 0)
106 }
107 #[doc = "Bit 16"]
108 #[inline(always)]
109 pub fn reg_gpio_33_ie(&self) -> REG_GPIO_33_IE_R {
110 REG_GPIO_33_IE_R::new(((self.bits >> 16) & 1) != 0)
111 }
112 #[doc = "Bit 17"]
113 #[inline(always)]
114 pub fn reg_gpio_33_smt(&self) -> REG_GPIO_33_SMT_R {
115 REG_GPIO_33_SMT_R::new(((self.bits >> 17) & 1) != 0)
116 }
117 #[doc = "Bits 18:19"]
118 #[inline(always)]
119 pub fn reg_gpio_33_drv(&self) -> REG_GPIO_33_DRV_R {
120 REG_GPIO_33_DRV_R::new(((self.bits >> 18) & 3) as u8)
121 }
122 #[doc = "Bit 20"]
123 #[inline(always)]
124 pub fn reg_gpio_33_pu(&self) -> REG_GPIO_33_PU_R {
125 REG_GPIO_33_PU_R::new(((self.bits >> 20) & 1) != 0)
126 }
127 #[doc = "Bit 21"]
128 #[inline(always)]
129 pub fn reg_gpio_33_pd(&self) -> REG_GPIO_33_PD_R {
130 REG_GPIO_33_PD_R::new(((self.bits >> 21) & 1) != 0)
131 }
132}
133impl W {
134 #[doc = "Bit 0"]
135 #[inline(always)]
136 #[must_use]
137 pub fn reg_gpio_32_ie(&mut self) -> REG_GPIO_32_IE_W<0> {
138 REG_GPIO_32_IE_W::new(self)
139 }
140 #[doc = "Bit 1"]
141 #[inline(always)]
142 #[must_use]
143 pub fn reg_gpio_32_smt(&mut self) -> REG_GPIO_32_SMT_W<1> {
144 REG_GPIO_32_SMT_W::new(self)
145 }
146 #[doc = "Bits 2:3"]
147 #[inline(always)]
148 #[must_use]
149 pub fn reg_gpio_32_drv(&mut self) -> REG_GPIO_32_DRV_W<2> {
150 REG_GPIO_32_DRV_W::new(self)
151 }
152 #[doc = "Bit 4"]
153 #[inline(always)]
154 #[must_use]
155 pub fn reg_gpio_32_pu(&mut self) -> REG_GPIO_32_PU_W<4> {
156 REG_GPIO_32_PU_W::new(self)
157 }
158 #[doc = "Bit 5"]
159 #[inline(always)]
160 #[must_use]
161 pub fn reg_gpio_32_pd(&mut self) -> REG_GPIO_32_PD_W<5> {
162 REG_GPIO_32_PD_W::new(self)
163 }
164 #[doc = "Bit 16"]
165 #[inline(always)]
166 #[must_use]
167 pub fn reg_gpio_33_ie(&mut self) -> REG_GPIO_33_IE_W<16> {
168 REG_GPIO_33_IE_W::new(self)
169 }
170 #[doc = "Bit 17"]
171 #[inline(always)]
172 #[must_use]
173 pub fn reg_gpio_33_smt(&mut self) -> REG_GPIO_33_SMT_W<17> {
174 REG_GPIO_33_SMT_W::new(self)
175 }
176 #[doc = "Bits 18:19"]
177 #[inline(always)]
178 #[must_use]
179 pub fn reg_gpio_33_drv(&mut self) -> REG_GPIO_33_DRV_W<18> {
180 REG_GPIO_33_DRV_W::new(self)
181 }
182 #[doc = "Bit 20"]
183 #[inline(always)]
184 #[must_use]
185 pub fn reg_gpio_33_pu(&mut self) -> REG_GPIO_33_PU_W<20> {
186 REG_GPIO_33_PU_W::new(self)
187 }
188 #[doc = "Bit 21"]
189 #[inline(always)]
190 #[must_use]
191 pub fn reg_gpio_33_pd(&mut self) -> REG_GPIO_33_PD_W<21> {
192 REG_GPIO_33_PD_W::new(self)
193 }
194 #[doc = "Writes raw bits to the register."]
195 #[inline(always)]
196 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
197 self.0.bits(bits);
198 self
199 }
200}
201#[doc = "GPIO_CFGCTL16.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_cfgctl16](index.html) module"]
202pub struct GPIO_CFGCTL16_SPEC;
203impl crate::RegisterSpec for GPIO_CFGCTL16_SPEC {
204 type Ux = u32;
205}
206#[doc = "`read()` method returns [gpio_cfgctl16::R](R) reader structure"]
207impl crate::Readable for GPIO_CFGCTL16_SPEC {
208 type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [gpio_cfgctl16::W](W) writer structure"]
211impl crate::Writable for GPIO_CFGCTL16_SPEC {
212 type Writer = W;
213 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
214 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
215}
216#[doc = "`reset()` method sets GPIO_CFGCTL16 to value 0"]
217impl crate::Resettable for GPIO_CFGCTL16_SPEC {
218 const RESET_VALUE: Self::Ux = 0;
219}