bl702_pac/glb/
gpio_cfgctl13.rs

1#[doc = "Register `GPIO_CFGCTL13` reader"]
2pub struct R(crate::R<GPIO_CFGCTL13_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<GPIO_CFGCTL13_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<GPIO_CFGCTL13_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<GPIO_CFGCTL13_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `GPIO_CFGCTL13` writer"]
17pub struct W(crate::W<GPIO_CFGCTL13_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<GPIO_CFGCTL13_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<GPIO_CFGCTL13_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<GPIO_CFGCTL13_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `reg_gpio_26_ie` reader - "]
38pub type REG_GPIO_26_IE_R = crate::BitReader<bool>;
39#[doc = "Field `reg_gpio_26_ie` writer - "]
40pub type REG_GPIO_26_IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
41#[doc = "Field `reg_gpio_26_smt` reader - "]
42pub type REG_GPIO_26_SMT_R = crate::BitReader<bool>;
43#[doc = "Field `reg_gpio_26_smt` writer - "]
44pub type REG_GPIO_26_SMT_W<'a, const O: u8> =
45    crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
46#[doc = "Field `reg_gpio_26_drv` reader - "]
47pub type REG_GPIO_26_DRV_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `reg_gpio_26_drv` writer - "]
49pub type REG_GPIO_26_DRV_W<'a, const O: u8> =
50    crate::FieldWriter<'a, u32, GPIO_CFGCTL13_SPEC, u8, u8, 2, O>;
51#[doc = "Field `reg_gpio_26_pu` reader - "]
52pub type REG_GPIO_26_PU_R = crate::BitReader<bool>;
53#[doc = "Field `reg_gpio_26_pu` writer - "]
54pub type REG_GPIO_26_PU_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
55#[doc = "Field `reg_gpio_26_pd` reader - "]
56pub type REG_GPIO_26_PD_R = crate::BitReader<bool>;
57#[doc = "Field `reg_gpio_26_pd` writer - "]
58pub type REG_GPIO_26_PD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
59#[doc = "Field `reg_gpio_26_func_sel` reader - "]
60pub type REG_GPIO_26_FUNC_SEL_R = crate::FieldReader<u8, u8>;
61#[doc = "Field `reg_gpio_26_func_sel` writer - "]
62pub type REG_GPIO_26_FUNC_SEL_W<'a, const O: u8> =
63    crate::FieldWriter<'a, u32, GPIO_CFGCTL13_SPEC, u8, u8, 5, O>;
64#[doc = "Field `reg_gpio_27_ie` reader - "]
65pub type REG_GPIO_27_IE_R = crate::BitReader<bool>;
66#[doc = "Field `reg_gpio_27_ie` writer - "]
67pub type REG_GPIO_27_IE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
68#[doc = "Field `reg_gpio_27_smt` reader - "]
69pub type REG_GPIO_27_SMT_R = crate::BitReader<bool>;
70#[doc = "Field `reg_gpio_27_smt` writer - "]
71pub type REG_GPIO_27_SMT_W<'a, const O: u8> =
72    crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
73#[doc = "Field `reg_gpio_27_drv` reader - "]
74pub type REG_GPIO_27_DRV_R = crate::FieldReader<u8, u8>;
75#[doc = "Field `reg_gpio_27_drv` writer - "]
76pub type REG_GPIO_27_DRV_W<'a, const O: u8> =
77    crate::FieldWriter<'a, u32, GPIO_CFGCTL13_SPEC, u8, u8, 2, O>;
78#[doc = "Field `reg_gpio_27_pu` reader - "]
79pub type REG_GPIO_27_PU_R = crate::BitReader<bool>;
80#[doc = "Field `reg_gpio_27_pu` writer - "]
81pub type REG_GPIO_27_PU_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
82#[doc = "Field `reg_gpio_27_pd` reader - "]
83pub type REG_GPIO_27_PD_R = crate::BitReader<bool>;
84#[doc = "Field `reg_gpio_27_pd` writer - "]
85pub type REG_GPIO_27_PD_W<'a, const O: u8> = crate::BitWriter<'a, u32, GPIO_CFGCTL13_SPEC, bool, O>;
86#[doc = "Field `reg_gpio_27_func_sel` reader - "]
87pub type REG_GPIO_27_FUNC_SEL_R = crate::FieldReader<u8, u8>;
88#[doc = "Field `reg_gpio_27_func_sel` writer - "]
89pub type REG_GPIO_27_FUNC_SEL_W<'a, const O: u8> =
90    crate::FieldWriter<'a, u32, GPIO_CFGCTL13_SPEC, u8, u8, 5, O>;
91impl R {
92    #[doc = "Bit 0"]
93    #[inline(always)]
94    pub fn reg_gpio_26_ie(&self) -> REG_GPIO_26_IE_R {
95        REG_GPIO_26_IE_R::new((self.bits & 1) != 0)
96    }
97    #[doc = "Bit 1"]
98    #[inline(always)]
99    pub fn reg_gpio_26_smt(&self) -> REG_GPIO_26_SMT_R {
100        REG_GPIO_26_SMT_R::new(((self.bits >> 1) & 1) != 0)
101    }
102    #[doc = "Bits 2:3"]
103    #[inline(always)]
104    pub fn reg_gpio_26_drv(&self) -> REG_GPIO_26_DRV_R {
105        REG_GPIO_26_DRV_R::new(((self.bits >> 2) & 3) as u8)
106    }
107    #[doc = "Bit 4"]
108    #[inline(always)]
109    pub fn reg_gpio_26_pu(&self) -> REG_GPIO_26_PU_R {
110        REG_GPIO_26_PU_R::new(((self.bits >> 4) & 1) != 0)
111    }
112    #[doc = "Bit 5"]
113    #[inline(always)]
114    pub fn reg_gpio_26_pd(&self) -> REG_GPIO_26_PD_R {
115        REG_GPIO_26_PD_R::new(((self.bits >> 5) & 1) != 0)
116    }
117    #[doc = "Bits 8:12"]
118    #[inline(always)]
119    pub fn reg_gpio_26_func_sel(&self) -> REG_GPIO_26_FUNC_SEL_R {
120        REG_GPIO_26_FUNC_SEL_R::new(((self.bits >> 8) & 0x1f) as u8)
121    }
122    #[doc = "Bit 16"]
123    #[inline(always)]
124    pub fn reg_gpio_27_ie(&self) -> REG_GPIO_27_IE_R {
125        REG_GPIO_27_IE_R::new(((self.bits >> 16) & 1) != 0)
126    }
127    #[doc = "Bit 17"]
128    #[inline(always)]
129    pub fn reg_gpio_27_smt(&self) -> REG_GPIO_27_SMT_R {
130        REG_GPIO_27_SMT_R::new(((self.bits >> 17) & 1) != 0)
131    }
132    #[doc = "Bits 18:19"]
133    #[inline(always)]
134    pub fn reg_gpio_27_drv(&self) -> REG_GPIO_27_DRV_R {
135        REG_GPIO_27_DRV_R::new(((self.bits >> 18) & 3) as u8)
136    }
137    #[doc = "Bit 20"]
138    #[inline(always)]
139    pub fn reg_gpio_27_pu(&self) -> REG_GPIO_27_PU_R {
140        REG_GPIO_27_PU_R::new(((self.bits >> 20) & 1) != 0)
141    }
142    #[doc = "Bit 21"]
143    #[inline(always)]
144    pub fn reg_gpio_27_pd(&self) -> REG_GPIO_27_PD_R {
145        REG_GPIO_27_PD_R::new(((self.bits >> 21) & 1) != 0)
146    }
147    #[doc = "Bits 24:28"]
148    #[inline(always)]
149    pub fn reg_gpio_27_func_sel(&self) -> REG_GPIO_27_FUNC_SEL_R {
150        REG_GPIO_27_FUNC_SEL_R::new(((self.bits >> 24) & 0x1f) as u8)
151    }
152}
153impl W {
154    #[doc = "Bit 0"]
155    #[inline(always)]
156    #[must_use]
157    pub fn reg_gpio_26_ie(&mut self) -> REG_GPIO_26_IE_W<0> {
158        REG_GPIO_26_IE_W::new(self)
159    }
160    #[doc = "Bit 1"]
161    #[inline(always)]
162    #[must_use]
163    pub fn reg_gpio_26_smt(&mut self) -> REG_GPIO_26_SMT_W<1> {
164        REG_GPIO_26_SMT_W::new(self)
165    }
166    #[doc = "Bits 2:3"]
167    #[inline(always)]
168    #[must_use]
169    pub fn reg_gpio_26_drv(&mut self) -> REG_GPIO_26_DRV_W<2> {
170        REG_GPIO_26_DRV_W::new(self)
171    }
172    #[doc = "Bit 4"]
173    #[inline(always)]
174    #[must_use]
175    pub fn reg_gpio_26_pu(&mut self) -> REG_GPIO_26_PU_W<4> {
176        REG_GPIO_26_PU_W::new(self)
177    }
178    #[doc = "Bit 5"]
179    #[inline(always)]
180    #[must_use]
181    pub fn reg_gpio_26_pd(&mut self) -> REG_GPIO_26_PD_W<5> {
182        REG_GPIO_26_PD_W::new(self)
183    }
184    #[doc = "Bits 8:12"]
185    #[inline(always)]
186    #[must_use]
187    pub fn reg_gpio_26_func_sel(&mut self) -> REG_GPIO_26_FUNC_SEL_W<8> {
188        REG_GPIO_26_FUNC_SEL_W::new(self)
189    }
190    #[doc = "Bit 16"]
191    #[inline(always)]
192    #[must_use]
193    pub fn reg_gpio_27_ie(&mut self) -> REG_GPIO_27_IE_W<16> {
194        REG_GPIO_27_IE_W::new(self)
195    }
196    #[doc = "Bit 17"]
197    #[inline(always)]
198    #[must_use]
199    pub fn reg_gpio_27_smt(&mut self) -> REG_GPIO_27_SMT_W<17> {
200        REG_GPIO_27_SMT_W::new(self)
201    }
202    #[doc = "Bits 18:19"]
203    #[inline(always)]
204    #[must_use]
205    pub fn reg_gpio_27_drv(&mut self) -> REG_GPIO_27_DRV_W<18> {
206        REG_GPIO_27_DRV_W::new(self)
207    }
208    #[doc = "Bit 20"]
209    #[inline(always)]
210    #[must_use]
211    pub fn reg_gpio_27_pu(&mut self) -> REG_GPIO_27_PU_W<20> {
212        REG_GPIO_27_PU_W::new(self)
213    }
214    #[doc = "Bit 21"]
215    #[inline(always)]
216    #[must_use]
217    pub fn reg_gpio_27_pd(&mut self) -> REG_GPIO_27_PD_W<21> {
218        REG_GPIO_27_PD_W::new(self)
219    }
220    #[doc = "Bits 24:28"]
221    #[inline(always)]
222    #[must_use]
223    pub fn reg_gpio_27_func_sel(&mut self) -> REG_GPIO_27_FUNC_SEL_W<24> {
224        REG_GPIO_27_FUNC_SEL_W::new(self)
225    }
226    #[doc = "Writes raw bits to the register."]
227    #[inline(always)]
228    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
229        self.0.bits(bits);
230        self
231    }
232}
233#[doc = "GPIO_CFGCTL13.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gpio_cfgctl13](index.html) module"]
234pub struct GPIO_CFGCTL13_SPEC;
235impl crate::RegisterSpec for GPIO_CFGCTL13_SPEC {
236    type Ux = u32;
237}
238#[doc = "`read()` method returns [gpio_cfgctl13::R](R) reader structure"]
239impl crate::Readable for GPIO_CFGCTL13_SPEC {
240    type Reader = R;
241}
242#[doc = "`write(|w| ..)` method takes [gpio_cfgctl13::W](W) writer structure"]
243impl crate::Writable for GPIO_CFGCTL13_SPEC {
244    type Writer = W;
245    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
246    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
247}
248#[doc = "`reset()` method sets GPIO_CFGCTL13 to value 0"]
249impl crate::Resettable for GPIO_CFGCTL13_SPEC {
250    const RESET_VALUE: Self::Ux = 0;
251}
bl702_pac/glb/gpio_cfgctl13.rs

bl702_pac/glb/
gpio_cfgctl13.rs
