1#[doc = "Register `glb_parm` reader"]
2pub struct R(crate::R<GLB_PARM_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<GLB_PARM_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<GLB_PARM_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<GLB_PARM_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `glb_parm` writer"]
17pub struct W(crate::W<GLB_PARM_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<GLB_PARM_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<GLB_PARM_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<GLB_PARM_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `jtag_swap_set` reader - "]
38pub type JTAG_SWAP_SET_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `jtag_swap_set` writer - "]
40pub type JTAG_SWAP_SET_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, GLB_PARM_SPEC, u8, u8, 8, O>;
42#[doc = "Field `cfg_sflash2_swap_io0_io3` reader - "]
43pub type CFG_SFLASH2_SWAP_IO0_IO3_R = crate::BitReader<bool>;
44#[doc = "Field `cfg_sflash2_swap_io0_io3` writer - "]
45pub type CFG_SFLASH2_SWAP_IO0_IO3_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
47#[doc = "Field `cfg_sflash2_swap_cs_io2` reader - "]
48pub type CFG_SFLASH2_SWAP_CS_IO2_R = crate::BitReader<bool>;
49#[doc = "Field `cfg_sflash2_swap_cs_io2` writer - "]
50pub type CFG_SFLASH2_SWAP_CS_IO2_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
52#[doc = "Field `cfg_flash_scenario` reader - "]
53pub type CFG_FLASH_SCENARIO_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `cfg_flash_scenario` writer - "]
55pub type CFG_FLASH_SCENARIO_W<'a, const O: u8> =
56 crate::FieldWriter<'a, u32, GLB_PARM_SPEC, u8, u8, 2, O>;
57#[doc = "Field `reg_spi_0_master_mode` reader - "]
58pub type REG_SPI_0_MASTER_MODE_R = crate::BitReader<bool>;
59#[doc = "Field `reg_spi_0_master_mode` writer - "]
60pub type REG_SPI_0_MASTER_MODE_W<'a, const O: u8> =
61 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
62#[doc = "Field `reg_spi_0_swap` reader - "]
63pub type REG_SPI_0_SWAP_R = crate::BitReader<bool>;
64#[doc = "Field `reg_spi_0_swap` writer - "]
65pub type REG_SPI_0_SWAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
66#[doc = "Field `reg_cci_use_jtag_pin` reader - "]
67pub type REG_CCI_USE_JTAG_PIN_R = crate::BitReader<bool>;
68#[doc = "Field `reg_cci_use_jtag_pin` writer - "]
69pub type REG_CCI_USE_JTAG_PIN_W<'a, const O: u8> =
70 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
71#[doc = "Field `p1_adc_test_with_cci` reader - "]
72pub type P1_ADC_TEST_WITH_CCI_R = crate::BitReader<bool>;
73#[doc = "Field `p1_adc_test_with_cci` writer - "]
74pub type P1_ADC_TEST_WITH_CCI_W<'a, const O: u8> =
75 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
76#[doc = "Field `p2_dac_test_with_cci` reader - "]
77pub type P2_DAC_TEST_WITH_CCI_R = crate::BitReader<bool>;
78#[doc = "Field `p2_dac_test_with_cci` writer - "]
79pub type P2_DAC_TEST_WITH_CCI_W<'a, const O: u8> =
80 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
81#[doc = "Field `p3_cci_use_io_0_2_7` reader - "]
82pub type P3_CCI_USE_IO_0_2_7_R = crate::BitReader<bool>;
83#[doc = "Field `p3_cci_use_io_0_2_7` writer - "]
84pub type P3_CCI_USE_IO_0_2_7_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
85#[doc = "Field `p4_adc_test_with_jtag` reader - "]
86pub type P4_ADC_TEST_WITH_JTAG_R = crate::BitReader<bool>;
87#[doc = "Field `p4_adc_test_with_jtag` writer - "]
88pub type P4_ADC_TEST_WITH_JTAG_W<'a, const O: u8> =
89 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
90#[doc = "Field `p5_dac_test_with_jtag` reader - "]
91pub type P5_DAC_TEST_WITH_JTAG_R = crate::BitReader<bool>;
92#[doc = "Field `p5_dac_test_with_jtag` writer - "]
93pub type P5_DAC_TEST_WITH_JTAG_W<'a, const O: u8> =
94 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
95#[doc = "Field `p6_jtag_use_io_0_2_7` reader - "]
96pub type P6_JTAG_USE_IO_0_2_7_R = crate::BitReader<bool>;
97#[doc = "Field `p6_jtag_use_io_0_2_7` writer - "]
98pub type P6_JTAG_USE_IO_0_2_7_W<'a, const O: u8> =
99 crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
100#[doc = "Field `uart_swap_set` reader - "]
101pub type UART_SWAP_SET_R = crate::FieldReader<u8, u8>;
102#[doc = "Field `uart_swap_set` writer - "]
103pub type UART_SWAP_SET_W<'a, const O: u8> =
104 crate::FieldWriter<'a, u32, GLB_PARM_SPEC, u8, u8, 4, O>;
105#[doc = "Field `reg_kys_drv_val` reader - "]
106pub type REG_KYS_DRV_VAL_R = crate::BitReader<bool>;
107#[doc = "Field `reg_kys_drv_val` writer - "]
108pub type REG_KYS_DRV_VAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
109#[doc = "Field `reg_ext_rst_smt` reader - "]
110pub type REG_EXT_RST_SMT_R = crate::BitReader<bool>;
111#[doc = "Field `reg_ext_rst_smt` writer - "]
112pub type REG_EXT_RST_SMT_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
113#[doc = "Field `pin_sel_emac_cam` reader - "]
114pub type PIN_SEL_EMAC_CAM_R = crate::BitReader<bool>;
115#[doc = "Field `pin_sel_emac_cam` writer - "]
116pub type PIN_SEL_EMAC_CAM_W<'a, const O: u8> = crate::BitWriter<'a, u32, GLB_PARM_SPEC, bool, O>;
117impl R {
118 #[doc = "Bits 0:7"]
119 #[inline(always)]
120 pub fn jtag_swap_set(&self) -> JTAG_SWAP_SET_R {
121 JTAG_SWAP_SET_R::new((self.bits & 0xff) as u8)
122 }
123 #[doc = "Bit 8"]
124 #[inline(always)]
125 pub fn cfg_sflash2_swap_io0_io3(&self) -> CFG_SFLASH2_SWAP_IO0_IO3_R {
126 CFG_SFLASH2_SWAP_IO0_IO3_R::new(((self.bits >> 8) & 1) != 0)
127 }
128 #[doc = "Bit 9"]
129 #[inline(always)]
130 pub fn cfg_sflash2_swap_cs_io2(&self) -> CFG_SFLASH2_SWAP_CS_IO2_R {
131 CFG_SFLASH2_SWAP_CS_IO2_R::new(((self.bits >> 9) & 1) != 0)
132 }
133 #[doc = "Bits 10:11"]
134 #[inline(always)]
135 pub fn cfg_flash_scenario(&self) -> CFG_FLASH_SCENARIO_R {
136 CFG_FLASH_SCENARIO_R::new(((self.bits >> 10) & 3) as u8)
137 }
138 #[doc = "Bit 12"]
139 #[inline(always)]
140 pub fn reg_spi_0_master_mode(&self) -> REG_SPI_0_MASTER_MODE_R {
141 REG_SPI_0_MASTER_MODE_R::new(((self.bits >> 12) & 1) != 0)
142 }
143 #[doc = "Bit 13"]
144 #[inline(always)]
145 pub fn reg_spi_0_swap(&self) -> REG_SPI_0_SWAP_R {
146 REG_SPI_0_SWAP_R::new(((self.bits >> 13) & 1) != 0)
147 }
148 #[doc = "Bit 16"]
149 #[inline(always)]
150 pub fn reg_cci_use_jtag_pin(&self) -> REG_CCI_USE_JTAG_PIN_R {
151 REG_CCI_USE_JTAG_PIN_R::new(((self.bits >> 16) & 1) != 0)
152 }
153 #[doc = "Bit 17"]
154 #[inline(always)]
155 pub fn p1_adc_test_with_cci(&self) -> P1_ADC_TEST_WITH_CCI_R {
156 P1_ADC_TEST_WITH_CCI_R::new(((self.bits >> 17) & 1) != 0)
157 }
158 #[doc = "Bit 18"]
159 #[inline(always)]
160 pub fn p2_dac_test_with_cci(&self) -> P2_DAC_TEST_WITH_CCI_R {
161 P2_DAC_TEST_WITH_CCI_R::new(((self.bits >> 18) & 1) != 0)
162 }
163 #[doc = "Bit 19"]
164 #[inline(always)]
165 pub fn p3_cci_use_io_0_2_7(&self) -> P3_CCI_USE_IO_0_2_7_R {
166 P3_CCI_USE_IO_0_2_7_R::new(((self.bits >> 19) & 1) != 0)
167 }
168 #[doc = "Bit 20"]
169 #[inline(always)]
170 pub fn p4_adc_test_with_jtag(&self) -> P4_ADC_TEST_WITH_JTAG_R {
171 P4_ADC_TEST_WITH_JTAG_R::new(((self.bits >> 20) & 1) != 0)
172 }
173 #[doc = "Bit 21"]
174 #[inline(always)]
175 pub fn p5_dac_test_with_jtag(&self) -> P5_DAC_TEST_WITH_JTAG_R {
176 P5_DAC_TEST_WITH_JTAG_R::new(((self.bits >> 21) & 1) != 0)
177 }
178 #[doc = "Bit 23"]
179 #[inline(always)]
180 pub fn p6_jtag_use_io_0_2_7(&self) -> P6_JTAG_USE_IO_0_2_7_R {
181 P6_JTAG_USE_IO_0_2_7_R::new(((self.bits >> 23) & 1) != 0)
182 }
183 #[doc = "Bits 24:27"]
184 #[inline(always)]
185 pub fn uart_swap_set(&self) -> UART_SWAP_SET_R {
186 UART_SWAP_SET_R::new(((self.bits >> 24) & 0x0f) as u8)
187 }
188 #[doc = "Bit 29"]
189 #[inline(always)]
190 pub fn reg_kys_drv_val(&self) -> REG_KYS_DRV_VAL_R {
191 REG_KYS_DRV_VAL_R::new(((self.bits >> 29) & 1) != 0)
192 }
193 #[doc = "Bit 30"]
194 #[inline(always)]
195 pub fn reg_ext_rst_smt(&self) -> REG_EXT_RST_SMT_R {
196 REG_EXT_RST_SMT_R::new(((self.bits >> 30) & 1) != 0)
197 }
198 #[doc = "Bit 31"]
199 #[inline(always)]
200 pub fn pin_sel_emac_cam(&self) -> PIN_SEL_EMAC_CAM_R {
201 PIN_SEL_EMAC_CAM_R::new(((self.bits >> 31) & 1) != 0)
202 }
203}
204impl W {
205 #[doc = "Bits 0:7"]
206 #[inline(always)]
207 #[must_use]
208 pub fn jtag_swap_set(&mut self) -> JTAG_SWAP_SET_W<0> {
209 JTAG_SWAP_SET_W::new(self)
210 }
211 #[doc = "Bit 8"]
212 #[inline(always)]
213 #[must_use]
214 pub fn cfg_sflash2_swap_io0_io3(&mut self) -> CFG_SFLASH2_SWAP_IO0_IO3_W<8> {
215 CFG_SFLASH2_SWAP_IO0_IO3_W::new(self)
216 }
217 #[doc = "Bit 9"]
218 #[inline(always)]
219 #[must_use]
220 pub fn cfg_sflash2_swap_cs_io2(&mut self) -> CFG_SFLASH2_SWAP_CS_IO2_W<9> {
221 CFG_SFLASH2_SWAP_CS_IO2_W::new(self)
222 }
223 #[doc = "Bits 10:11"]
224 #[inline(always)]
225 #[must_use]
226 pub fn cfg_flash_scenario(&mut self) -> CFG_FLASH_SCENARIO_W<10> {
227 CFG_FLASH_SCENARIO_W::new(self)
228 }
229 #[doc = "Bit 12"]
230 #[inline(always)]
231 #[must_use]
232 pub fn reg_spi_0_master_mode(&mut self) -> REG_SPI_0_MASTER_MODE_W<12> {
233 REG_SPI_0_MASTER_MODE_W::new(self)
234 }
235 #[doc = "Bit 13"]
236 #[inline(always)]
237 #[must_use]
238 pub fn reg_spi_0_swap(&mut self) -> REG_SPI_0_SWAP_W<13> {
239 REG_SPI_0_SWAP_W::new(self)
240 }
241 #[doc = "Bit 16"]
242 #[inline(always)]
243 #[must_use]
244 pub fn reg_cci_use_jtag_pin(&mut self) -> REG_CCI_USE_JTAG_PIN_W<16> {
245 REG_CCI_USE_JTAG_PIN_W::new(self)
246 }
247 #[doc = "Bit 17"]
248 #[inline(always)]
249 #[must_use]
250 pub fn p1_adc_test_with_cci(&mut self) -> P1_ADC_TEST_WITH_CCI_W<17> {
251 P1_ADC_TEST_WITH_CCI_W::new(self)
252 }
253 #[doc = "Bit 18"]
254 #[inline(always)]
255 #[must_use]
256 pub fn p2_dac_test_with_cci(&mut self) -> P2_DAC_TEST_WITH_CCI_W<18> {
257 P2_DAC_TEST_WITH_CCI_W::new(self)
258 }
259 #[doc = "Bit 19"]
260 #[inline(always)]
261 #[must_use]
262 pub fn p3_cci_use_io_0_2_7(&mut self) -> P3_CCI_USE_IO_0_2_7_W<19> {
263 P3_CCI_USE_IO_0_2_7_W::new(self)
264 }
265 #[doc = "Bit 20"]
266 #[inline(always)]
267 #[must_use]
268 pub fn p4_adc_test_with_jtag(&mut self) -> P4_ADC_TEST_WITH_JTAG_W<20> {
269 P4_ADC_TEST_WITH_JTAG_W::new(self)
270 }
271 #[doc = "Bit 21"]
272 #[inline(always)]
273 #[must_use]
274 pub fn p5_dac_test_with_jtag(&mut self) -> P5_DAC_TEST_WITH_JTAG_W<21> {
275 P5_DAC_TEST_WITH_JTAG_W::new(self)
276 }
277 #[doc = "Bit 23"]
278 #[inline(always)]
279 #[must_use]
280 pub fn p6_jtag_use_io_0_2_7(&mut self) -> P6_JTAG_USE_IO_0_2_7_W<23> {
281 P6_JTAG_USE_IO_0_2_7_W::new(self)
282 }
283 #[doc = "Bits 24:27"]
284 #[inline(always)]
285 #[must_use]
286 pub fn uart_swap_set(&mut self) -> UART_SWAP_SET_W<24> {
287 UART_SWAP_SET_W::new(self)
288 }
289 #[doc = "Bit 29"]
290 #[inline(always)]
291 #[must_use]
292 pub fn reg_kys_drv_val(&mut self) -> REG_KYS_DRV_VAL_W<29> {
293 REG_KYS_DRV_VAL_W::new(self)
294 }
295 #[doc = "Bit 30"]
296 #[inline(always)]
297 #[must_use]
298 pub fn reg_ext_rst_smt(&mut self) -> REG_EXT_RST_SMT_W<30> {
299 REG_EXT_RST_SMT_W::new(self)
300 }
301 #[doc = "Bit 31"]
302 #[inline(always)]
303 #[must_use]
304 pub fn pin_sel_emac_cam(&mut self) -> PIN_SEL_EMAC_CAM_W<31> {
305 PIN_SEL_EMAC_CAM_W::new(self)
306 }
307 #[doc = "Writes raw bits to the register."]
308 #[inline(always)]
309 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
310 self.0.bits(bits);
311 self
312 }
313}
314#[doc = "glb_parm.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [glb_parm](index.html) module"]
315pub struct GLB_PARM_SPEC;
316impl crate::RegisterSpec for GLB_PARM_SPEC {
317 type Ux = u32;
318}
319#[doc = "`read()` method returns [glb_parm::R](R) reader structure"]
320impl crate::Readable for GLB_PARM_SPEC {
321 type Reader = R;
322}
323#[doc = "`write(|w| ..)` method takes [glb_parm::W](W) writer structure"]
324impl crate::Writable for GLB_PARM_SPEC {
325 type Writer = W;
326 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
327 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
328}
329#[doc = "`reset()` method sets glb_parm to value 0"]
330impl crate::Resettable for GLB_PARM_SPEC {
331 const RESET_VALUE: Self::Ux = 0;
332}