bl702_pac/glb/
clk_cfg3.rs

1#[doc = "Register `clk_cfg3` reader"]
2pub struct R(crate::R<CLK_CFG3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLK_CFG3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLK_CFG3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLK_CFG3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `clk_cfg3` writer"]
17pub struct W(crate::W<CLK_CFG3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLK_CFG3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLK_CFG3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLK_CFG3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `spi_clk_div` reader - "]
38pub type SPI_CLK_DIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `spi_clk_div` writer - "]
40pub type SPI_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG3_SPEC, u8, u8, 5, O>;
41#[doc = "Field `cfg_sel_eth_ref_clk_o` reader - "]
42pub type CFG_SEL_ETH_REF_CLK_O_R = crate::BitReader<bool>;
43#[doc = "Field `cfg_sel_eth_ref_clk_o` writer - "]
44pub type CFG_SEL_ETH_REF_CLK_O_W<'a, const O: u8> =
45    crate::BitWriter<'a, u32, CLK_CFG3_SPEC, bool, O>;
46#[doc = "Field `cfg_inv_eth_ref_clk_o` reader - "]
47pub type CFG_INV_ETH_REF_CLK_O_R = crate::BitReader<bool>;
48#[doc = "Field `cfg_inv_eth_ref_clk_o` writer - "]
49pub type CFG_INV_ETH_REF_CLK_O_W<'a, const O: u8> =
50    crate::BitWriter<'a, u32, CLK_CFG3_SPEC, bool, O>;
51#[doc = "Field `cfg_inv_eth_tx_clk` reader - "]
52pub type CFG_INV_ETH_TX_CLK_R = crate::BitReader<bool>;
53#[doc = "Field `cfg_inv_eth_tx_clk` writer - "]
54pub type CFG_INV_ETH_TX_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG3_SPEC, bool, O>;
55#[doc = "Field `spi_clk_en` reader - "]
56pub type SPI_CLK_EN_R = crate::BitReader<bool>;
57#[doc = "Field `spi_clk_en` writer - "]
58pub type SPI_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG3_SPEC, bool, O>;
59#[doc = "Field `cfg_inv_rf_test_clk_o` reader - "]
60pub type CFG_INV_RF_TEST_CLK_O_R = crate::BitReader<bool>;
61#[doc = "Field `cfg_inv_rf_test_clk_o` writer - "]
62pub type CFG_INV_RF_TEST_CLK_O_W<'a, const O: u8> =
63    crate::BitWriter<'a, u32, CLK_CFG3_SPEC, bool, O>;
64#[doc = "Field `cfg_inv_eth_rx_clk` reader - "]
65pub type CFG_INV_ETH_RX_CLK_R = crate::BitReader<bool>;
66#[doc = "Field `cfg_inv_eth_rx_clk` writer - "]
67pub type CFG_INV_ETH_RX_CLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG3_SPEC, bool, O>;
68#[doc = "Field `i2c_clk_div` reader - "]
69pub type I2C_CLK_DIV_R = crate::FieldReader<u8, u8>;
70#[doc = "Field `i2c_clk_div` writer - "]
71pub type I2C_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG3_SPEC, u8, u8, 8, O>;
72#[doc = "Field `i2c_clk_en` reader - "]
73pub type I2C_CLK_EN_R = crate::BitReader<bool>;
74#[doc = "Field `i2c_clk_en` writer - "]
75pub type I2C_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG3_SPEC, bool, O>;
76#[doc = "Field `chip_clk_out_0_sel` reader - "]
77pub type CHIP_CLK_OUT_0_SEL_R = crate::FieldReader<u8, u8>;
78#[doc = "Field `chip_clk_out_0_sel` writer - "]
79pub type CHIP_CLK_OUT_0_SEL_W<'a, const O: u8> =
80    crate::FieldWriter<'a, u32, CLK_CFG3_SPEC, u8, u8, 2, O>;
81#[doc = "Field `chip_clk_out_1_sel` reader - "]
82pub type CHIP_CLK_OUT_1_SEL_R = crate::FieldReader<u8, u8>;
83#[doc = "Field `chip_clk_out_1_sel` writer - "]
84pub type CHIP_CLK_OUT_1_SEL_W<'a, const O: u8> =
85    crate::FieldWriter<'a, u32, CLK_CFG3_SPEC, u8, u8, 2, O>;
86impl R {
87    #[doc = "Bits 0:4"]
88    #[inline(always)]
89    pub fn spi_clk_div(&self) -> SPI_CLK_DIV_R {
90        SPI_CLK_DIV_R::new((self.bits & 0x1f) as u8)
91    }
92    #[doc = "Bit 5"]
93    #[inline(always)]
94    pub fn cfg_sel_eth_ref_clk_o(&self) -> CFG_SEL_ETH_REF_CLK_O_R {
95        CFG_SEL_ETH_REF_CLK_O_R::new(((self.bits >> 5) & 1) != 0)
96    }
97    #[doc = "Bit 6"]
98    #[inline(always)]
99    pub fn cfg_inv_eth_ref_clk_o(&self) -> CFG_INV_ETH_REF_CLK_O_R {
100        CFG_INV_ETH_REF_CLK_O_R::new(((self.bits >> 6) & 1) != 0)
101    }
102    #[doc = "Bit 7"]
103    #[inline(always)]
104    pub fn cfg_inv_eth_tx_clk(&self) -> CFG_INV_ETH_TX_CLK_R {
105        CFG_INV_ETH_TX_CLK_R::new(((self.bits >> 7) & 1) != 0)
106    }
107    #[doc = "Bit 8"]
108    #[inline(always)]
109    pub fn spi_clk_en(&self) -> SPI_CLK_EN_R {
110        SPI_CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
111    }
112    #[doc = "Bit 9"]
113    #[inline(always)]
114    pub fn cfg_inv_rf_test_clk_o(&self) -> CFG_INV_RF_TEST_CLK_O_R {
115        CFG_INV_RF_TEST_CLK_O_R::new(((self.bits >> 9) & 1) != 0)
116    }
117    #[doc = "Bit 10"]
118    #[inline(always)]
119    pub fn cfg_inv_eth_rx_clk(&self) -> CFG_INV_ETH_RX_CLK_R {
120        CFG_INV_ETH_RX_CLK_R::new(((self.bits >> 10) & 1) != 0)
121    }
122    #[doc = "Bits 16:23"]
123    #[inline(always)]
124    pub fn i2c_clk_div(&self) -> I2C_CLK_DIV_R {
125        I2C_CLK_DIV_R::new(((self.bits >> 16) & 0xff) as u8)
126    }
127    #[doc = "Bit 24"]
128    #[inline(always)]
129    pub fn i2c_clk_en(&self) -> I2C_CLK_EN_R {
130        I2C_CLK_EN_R::new(((self.bits >> 24) & 1) != 0)
131    }
132    #[doc = "Bits 28:29"]
133    #[inline(always)]
134    pub fn chip_clk_out_0_sel(&self) -> CHIP_CLK_OUT_0_SEL_R {
135        CHIP_CLK_OUT_0_SEL_R::new(((self.bits >> 28) & 3) as u8)
136    }
137    #[doc = "Bits 30:31"]
138    #[inline(always)]
139    pub fn chip_clk_out_1_sel(&self) -> CHIP_CLK_OUT_1_SEL_R {
140        CHIP_CLK_OUT_1_SEL_R::new(((self.bits >> 30) & 3) as u8)
141    }
142}
143impl W {
144    #[doc = "Bits 0:4"]
145    #[inline(always)]
146    #[must_use]
147    pub fn spi_clk_div(&mut self) -> SPI_CLK_DIV_W<0> {
148        SPI_CLK_DIV_W::new(self)
149    }
150    #[doc = "Bit 5"]
151    #[inline(always)]
152    #[must_use]
153    pub fn cfg_sel_eth_ref_clk_o(&mut self) -> CFG_SEL_ETH_REF_CLK_O_W<5> {
154        CFG_SEL_ETH_REF_CLK_O_W::new(self)
155    }
156    #[doc = "Bit 6"]
157    #[inline(always)]
158    #[must_use]
159    pub fn cfg_inv_eth_ref_clk_o(&mut self) -> CFG_INV_ETH_REF_CLK_O_W<6> {
160        CFG_INV_ETH_REF_CLK_O_W::new(self)
161    }
162    #[doc = "Bit 7"]
163    #[inline(always)]
164    #[must_use]
165    pub fn cfg_inv_eth_tx_clk(&mut self) -> CFG_INV_ETH_TX_CLK_W<7> {
166        CFG_INV_ETH_TX_CLK_W::new(self)
167    }
168    #[doc = "Bit 8"]
169    #[inline(always)]
170    #[must_use]
171    pub fn spi_clk_en(&mut self) -> SPI_CLK_EN_W<8> {
172        SPI_CLK_EN_W::new(self)
173    }
174    #[doc = "Bit 9"]
175    #[inline(always)]
176    #[must_use]
177    pub fn cfg_inv_rf_test_clk_o(&mut self) -> CFG_INV_RF_TEST_CLK_O_W<9> {
178        CFG_INV_RF_TEST_CLK_O_W::new(self)
179    }
180    #[doc = "Bit 10"]
181    #[inline(always)]
182    #[must_use]
183    pub fn cfg_inv_eth_rx_clk(&mut self) -> CFG_INV_ETH_RX_CLK_W<10> {
184        CFG_INV_ETH_RX_CLK_W::new(self)
185    }
186    #[doc = "Bits 16:23"]
187    #[inline(always)]
188    #[must_use]
189    pub fn i2c_clk_div(&mut self) -> I2C_CLK_DIV_W<16> {
190        I2C_CLK_DIV_W::new(self)
191    }
192    #[doc = "Bit 24"]
193    #[inline(always)]
194    #[must_use]
195    pub fn i2c_clk_en(&mut self) -> I2C_CLK_EN_W<24> {
196        I2C_CLK_EN_W::new(self)
197    }
198    #[doc = "Bits 28:29"]
199    #[inline(always)]
200    #[must_use]
201    pub fn chip_clk_out_0_sel(&mut self) -> CHIP_CLK_OUT_0_SEL_W<28> {
202        CHIP_CLK_OUT_0_SEL_W::new(self)
203    }
204    #[doc = "Bits 30:31"]
205    #[inline(always)]
206    #[must_use]
207    pub fn chip_clk_out_1_sel(&mut self) -> CHIP_CLK_OUT_1_SEL_W<30> {
208        CHIP_CLK_OUT_1_SEL_W::new(self)
209    }
210    #[doc = "Writes raw bits to the register."]
211    #[inline(always)]
212    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
213        self.0.bits(bits);
214        self
215    }
216}
217#[doc = "clk_cfg3.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg3](index.html) module"]
218pub struct CLK_CFG3_SPEC;
219impl crate::RegisterSpec for CLK_CFG3_SPEC {
220    type Ux = u32;
221}
222#[doc = "`read()` method returns [clk_cfg3::R](R) reader structure"]
223impl crate::Readable for CLK_CFG3_SPEC {
224    type Reader = R;
225}
226#[doc = "`write(|w| ..)` method takes [clk_cfg3::W](W) writer structure"]
227impl crate::Writable for CLK_CFG3_SPEC {
228    type Writer = W;
229    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
230    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
231}
232#[doc = "`reset()` method sets clk_cfg3 to value 0"]
233impl crate::Resettable for CLK_CFG3_SPEC {
234    const RESET_VALUE: Self::Ux = 0;
235}
bl702_pac/glb/clk_cfg3.rs

bl702_pac/glb/
clk_cfg3.rs
