bl702_pac/glb/
clk_cfg2.rs1#[doc = "Register `clk_cfg2` reader"]
2pub struct R(crate::R<CLK_CFG2_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLK_CFG2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLK_CFG2_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLK_CFG2_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `clk_cfg2` writer"]
17pub struct W(crate::W<CLK_CFG2_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLK_CFG2_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLK_CFG2_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLK_CFG2_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `uart_clk_div` reader - "]
38pub type UART_CLK_DIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `uart_clk_div` writer - "]
40pub type UART_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 3, O>;
41#[doc = "Field `uart_clk_en` reader - "]
42pub type UART_CLK_EN_R = crate::BitReader<bool>;
43#[doc = "Field `uart_clk_en` writer - "]
44pub type UART_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG2_SPEC, bool, O>;
45#[doc = "Field `hbn_uart_clk_sel` reader - "]
46pub type HBN_UART_CLK_SEL_R = crate::BitReader<bool>;
47#[doc = "Field `hbn_uart_clk_sel` writer - "]
48pub type HBN_UART_CLK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG2_SPEC, bool, O>;
49#[doc = "Field `sf_clk_div` reader - "]
50pub type SF_CLK_DIV_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `sf_clk_div` writer - "]
52pub type SF_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 3, O>;
53#[doc = "Field `sf_clk_en` reader - "]
54pub type SF_CLK_EN_R = crate::BitReader<bool>;
55#[doc = "Field `sf_clk_en` writer - "]
56pub type SF_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG2_SPEC, bool, O>;
57#[doc = "Field `sf_clk_sel` reader - "]
58pub type SF_CLK_SEL_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `sf_clk_sel` writer - "]
60pub type SF_CLK_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 2, O>;
61#[doc = "Field `sf_clk_sel2` reader - "]
62pub type SF_CLK_SEL2_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `sf_clk_sel2` writer - "]
64pub type SF_CLK_SEL2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 2, O>;
65#[doc = "Field `ir_clk_div` reader - "]
66pub type IR_CLK_DIV_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `ir_clk_div` writer - "]
68pub type IR_CLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 6, O>;
69#[doc = "Field `ir_clk_en` reader - "]
70pub type IR_CLK_EN_R = crate::BitReader<bool>;
71#[doc = "Field `ir_clk_en` writer - "]
72pub type IR_CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG2_SPEC, bool, O>;
73#[doc = "Field `dma_clk_en` reader - "]
74pub type DMA_CLK_EN_R = crate::FieldReader<u8, u8>;
75#[doc = "Field `dma_clk_en` writer - "]
76pub type DMA_CLK_EN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG2_SPEC, u8, u8, 8, O>;
77impl R {
78 #[doc = "Bits 0:2"]
79 #[inline(always)]
80 pub fn uart_clk_div(&self) -> UART_CLK_DIV_R {
81 UART_CLK_DIV_R::new((self.bits & 7) as u8)
82 }
83 #[doc = "Bit 4"]
84 #[inline(always)]
85 pub fn uart_clk_en(&self) -> UART_CLK_EN_R {
86 UART_CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
87 }
88 #[doc = "Bit 7"]
89 #[inline(always)]
90 pub fn hbn_uart_clk_sel(&self) -> HBN_UART_CLK_SEL_R {
91 HBN_UART_CLK_SEL_R::new(((self.bits >> 7) & 1) != 0)
92 }
93 #[doc = "Bits 8:10"]
94 #[inline(always)]
95 pub fn sf_clk_div(&self) -> SF_CLK_DIV_R {
96 SF_CLK_DIV_R::new(((self.bits >> 8) & 7) as u8)
97 }
98 #[doc = "Bit 11"]
99 #[inline(always)]
100 pub fn sf_clk_en(&self) -> SF_CLK_EN_R {
101 SF_CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
102 }
103 #[doc = "Bits 12:13"]
104 #[inline(always)]
105 pub fn sf_clk_sel(&self) -> SF_CLK_SEL_R {
106 SF_CLK_SEL_R::new(((self.bits >> 12) & 3) as u8)
107 }
108 #[doc = "Bits 14:15"]
109 #[inline(always)]
110 pub fn sf_clk_sel2(&self) -> SF_CLK_SEL2_R {
111 SF_CLK_SEL2_R::new(((self.bits >> 14) & 3) as u8)
112 }
113 #[doc = "Bits 16:21"]
114 #[inline(always)]
115 pub fn ir_clk_div(&self) -> IR_CLK_DIV_R {
116 IR_CLK_DIV_R::new(((self.bits >> 16) & 0x3f) as u8)
117 }
118 #[doc = "Bit 23"]
119 #[inline(always)]
120 pub fn ir_clk_en(&self) -> IR_CLK_EN_R {
121 IR_CLK_EN_R::new(((self.bits >> 23) & 1) != 0)
122 }
123 #[doc = "Bits 24:31"]
124 #[inline(always)]
125 pub fn dma_clk_en(&self) -> DMA_CLK_EN_R {
126 DMA_CLK_EN_R::new(((self.bits >> 24) & 0xff) as u8)
127 }
128}
129impl W {
130 #[doc = "Bits 0:2"]
131 #[inline(always)]
132 #[must_use]
133 pub fn uart_clk_div(&mut self) -> UART_CLK_DIV_W<0> {
134 UART_CLK_DIV_W::new(self)
135 }
136 #[doc = "Bit 4"]
137 #[inline(always)]
138 #[must_use]
139 pub fn uart_clk_en(&mut self) -> UART_CLK_EN_W<4> {
140 UART_CLK_EN_W::new(self)
141 }
142 #[doc = "Bit 7"]
143 #[inline(always)]
144 #[must_use]
145 pub fn hbn_uart_clk_sel(&mut self) -> HBN_UART_CLK_SEL_W<7> {
146 HBN_UART_CLK_SEL_W::new(self)
147 }
148 #[doc = "Bits 8:10"]
149 #[inline(always)]
150 #[must_use]
151 pub fn sf_clk_div(&mut self) -> SF_CLK_DIV_W<8> {
152 SF_CLK_DIV_W::new(self)
153 }
154 #[doc = "Bit 11"]
155 #[inline(always)]
156 #[must_use]
157 pub fn sf_clk_en(&mut self) -> SF_CLK_EN_W<11> {
158 SF_CLK_EN_W::new(self)
159 }
160 #[doc = "Bits 12:13"]
161 #[inline(always)]
162 #[must_use]
163 pub fn sf_clk_sel(&mut self) -> SF_CLK_SEL_W<12> {
164 SF_CLK_SEL_W::new(self)
165 }
166 #[doc = "Bits 14:15"]
167 #[inline(always)]
168 #[must_use]
169 pub fn sf_clk_sel2(&mut self) -> SF_CLK_SEL2_W<14> {
170 SF_CLK_SEL2_W::new(self)
171 }
172 #[doc = "Bits 16:21"]
173 #[inline(always)]
174 #[must_use]
175 pub fn ir_clk_div(&mut self) -> IR_CLK_DIV_W<16> {
176 IR_CLK_DIV_W::new(self)
177 }
178 #[doc = "Bit 23"]
179 #[inline(always)]
180 #[must_use]
181 pub fn ir_clk_en(&mut self) -> IR_CLK_EN_W<23> {
182 IR_CLK_EN_W::new(self)
183 }
184 #[doc = "Bits 24:31"]
185 #[inline(always)]
186 #[must_use]
187 pub fn dma_clk_en(&mut self) -> DMA_CLK_EN_W<24> {
188 DMA_CLK_EN_W::new(self)
189 }
190 #[doc = "Writes raw bits to the register."]
191 #[inline(always)]
192 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
193 self.0.bits(bits);
194 self
195 }
196}
197#[doc = "clk_cfg2.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg2](index.html) module"]
198pub struct CLK_CFG2_SPEC;
199impl crate::RegisterSpec for CLK_CFG2_SPEC {
200 type Ux = u32;
201}
202#[doc = "`read()` method returns [clk_cfg2::R](R) reader structure"]
203impl crate::Readable for CLK_CFG2_SPEC {
204 type Reader = R;
205}
206#[doc = "`write(|w| ..)` method takes [clk_cfg2::W](W) writer structure"]
207impl crate::Writable for CLK_CFG2_SPEC {
208 type Writer = W;
209 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
211}
212#[doc = "`reset()` method sets clk_cfg2 to value 0"]
213impl crate::Resettable for CLK_CFG2_SPEC {
214 const RESET_VALUE: Self::Ux = 0;
215}