bl702_pac/glb/
clk_cfg0.rs1#[doc = "Register `clk_cfg0` reader"]
2pub struct R(crate::R<CLK_CFG0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CLK_CFG0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CLK_CFG0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CLK_CFG0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `clk_cfg0` writer"]
17pub struct W(crate::W<CLK_CFG0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CLK_CFG0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CLK_CFG0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CLK_CFG0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `reg_pll_en` reader - "]
38pub type REG_PLL_EN_R = crate::BitReader<bool>;
39#[doc = "Field `reg_pll_en` writer - "]
40pub type REG_PLL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
41#[doc = "Field `reg_fclk_en` reader - "]
42pub type REG_FCLK_EN_R = crate::BitReader<bool>;
43#[doc = "Field `reg_fclk_en` writer - "]
44pub type REG_FCLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
45#[doc = "Field `reg_hclk_en` reader - "]
46pub type REG_HCLK_EN_R = crate::BitReader<bool>;
47#[doc = "Field `reg_hclk_en` writer - "]
48pub type REG_HCLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
49#[doc = "Field `reg_bclk_en` reader - "]
50pub type REG_BCLK_EN_R = crate::BitReader<bool>;
51#[doc = "Field `reg_bclk_en` writer - "]
52pub type REG_BCLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
53#[doc = "Field `reg_pll_sel` reader - "]
54pub type REG_PLL_SEL_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `reg_pll_sel` writer - "]
56pub type REG_PLL_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 2, O>;
57#[doc = "Field `hbn_root_clk_sel` reader - "]
58pub type HBN_ROOT_CLK_SEL_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `hbn_root_clk_sel` writer - "]
60pub type HBN_ROOT_CLK_SEL_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 2, O>;
62#[doc = "Field `reg_hclk_div` reader - "]
63pub type REG_HCLK_DIV_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `reg_hclk_div` writer - "]
65pub type REG_HCLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 8, O>;
66#[doc = "Field `reg_bclk_div` reader - "]
67pub type REG_BCLK_DIV_R = crate::FieldReader<u8, u8>;
68#[doc = "Field `reg_bclk_div` writer - "]
69pub type REG_BCLK_DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 8, O>;
70#[doc = "Field `fclk_sw_state` reader - "]
71pub type FCLK_SW_STATE_R = crate::FieldReader<u8, u8>;
72#[doc = "Field `fclk_sw_state` writer - "]
73pub type FCLK_SW_STATE_W<'a, const O: u8> =
74 crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 3, O>;
75#[doc = "Field `chip_rdy` reader - "]
76pub type CHIP_RDY_R = crate::BitReader<bool>;
77#[doc = "Field `chip_rdy` writer - "]
78pub type CHIP_RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLK_CFG0_SPEC, bool, O>;
79#[doc = "Field `glb_id` reader - "]
80pub type GLB_ID_R = crate::FieldReader<u8, u8>;
81#[doc = "Field `glb_id` writer - "]
82pub type GLB_ID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 4, O>;
83impl R {
84 #[doc = "Bit 0"]
85 #[inline(always)]
86 pub fn reg_pll_en(&self) -> REG_PLL_EN_R {
87 REG_PLL_EN_R::new((self.bits & 1) != 0)
88 }
89 #[doc = "Bit 1"]
90 #[inline(always)]
91 pub fn reg_fclk_en(&self) -> REG_FCLK_EN_R {
92 REG_FCLK_EN_R::new(((self.bits >> 1) & 1) != 0)
93 }
94 #[doc = "Bit 2"]
95 #[inline(always)]
96 pub fn reg_hclk_en(&self) -> REG_HCLK_EN_R {
97 REG_HCLK_EN_R::new(((self.bits >> 2) & 1) != 0)
98 }
99 #[doc = "Bit 3"]
100 #[inline(always)]
101 pub fn reg_bclk_en(&self) -> REG_BCLK_EN_R {
102 REG_BCLK_EN_R::new(((self.bits >> 3) & 1) != 0)
103 }
104 #[doc = "Bits 4:5"]
105 #[inline(always)]
106 pub fn reg_pll_sel(&self) -> REG_PLL_SEL_R {
107 REG_PLL_SEL_R::new(((self.bits >> 4) & 3) as u8)
108 }
109 #[doc = "Bits 6:7"]
110 #[inline(always)]
111 pub fn hbn_root_clk_sel(&self) -> HBN_ROOT_CLK_SEL_R {
112 HBN_ROOT_CLK_SEL_R::new(((self.bits >> 6) & 3) as u8)
113 }
114 #[doc = "Bits 8:15"]
115 #[inline(always)]
116 pub fn reg_hclk_div(&self) -> REG_HCLK_DIV_R {
117 REG_HCLK_DIV_R::new(((self.bits >> 8) & 0xff) as u8)
118 }
119 #[doc = "Bits 16:23"]
120 #[inline(always)]
121 pub fn reg_bclk_div(&self) -> REG_BCLK_DIV_R {
122 REG_BCLK_DIV_R::new(((self.bits >> 16) & 0xff) as u8)
123 }
124 #[doc = "Bits 24:26"]
125 #[inline(always)]
126 pub fn fclk_sw_state(&self) -> FCLK_SW_STATE_R {
127 FCLK_SW_STATE_R::new(((self.bits >> 24) & 7) as u8)
128 }
129 #[doc = "Bit 27"]
130 #[inline(always)]
131 pub fn chip_rdy(&self) -> CHIP_RDY_R {
132 CHIP_RDY_R::new(((self.bits >> 27) & 1) != 0)
133 }
134 #[doc = "Bits 28:31"]
135 #[inline(always)]
136 pub fn glb_id(&self) -> GLB_ID_R {
137 GLB_ID_R::new(((self.bits >> 28) & 0x0f) as u8)
138 }
139}
140impl W {
141 #[doc = "Bit 0"]
142 #[inline(always)]
143 #[must_use]
144 pub fn reg_pll_en(&mut self) -> REG_PLL_EN_W<0> {
145 REG_PLL_EN_W::new(self)
146 }
147 #[doc = "Bit 1"]
148 #[inline(always)]
149 #[must_use]
150 pub fn reg_fclk_en(&mut self) -> REG_FCLK_EN_W<1> {
151 REG_FCLK_EN_W::new(self)
152 }
153 #[doc = "Bit 2"]
154 #[inline(always)]
155 #[must_use]
156 pub fn reg_hclk_en(&mut self) -> REG_HCLK_EN_W<2> {
157 REG_HCLK_EN_W::new(self)
158 }
159 #[doc = "Bit 3"]
160 #[inline(always)]
161 #[must_use]
162 pub fn reg_bclk_en(&mut self) -> REG_BCLK_EN_W<3> {
163 REG_BCLK_EN_W::new(self)
164 }
165 #[doc = "Bits 4:5"]
166 #[inline(always)]
167 #[must_use]
168 pub fn reg_pll_sel(&mut self) -> REG_PLL_SEL_W<4> {
169 REG_PLL_SEL_W::new(self)
170 }
171 #[doc = "Bits 6:7"]
172 #[inline(always)]
173 #[must_use]
174 pub fn hbn_root_clk_sel(&mut self) -> HBN_ROOT_CLK_SEL_W<6> {
175 HBN_ROOT_CLK_SEL_W::new(self)
176 }
177 #[doc = "Bits 8:15"]
178 #[inline(always)]
179 #[must_use]
180 pub fn reg_hclk_div(&mut self) -> REG_HCLK_DIV_W<8> {
181 REG_HCLK_DIV_W::new(self)
182 }
183 #[doc = "Bits 16:23"]
184 #[inline(always)]
185 #[must_use]
186 pub fn reg_bclk_div(&mut self) -> REG_BCLK_DIV_W<16> {
187 REG_BCLK_DIV_W::new(self)
188 }
189 #[doc = "Bits 24:26"]
190 #[inline(always)]
191 #[must_use]
192 pub fn fclk_sw_state(&mut self) -> FCLK_SW_STATE_W<24> {
193 FCLK_SW_STATE_W::new(self)
194 }
195 #[doc = "Bit 27"]
196 #[inline(always)]
197 #[must_use]
198 pub fn chip_rdy(&mut self) -> CHIP_RDY_W<27> {
199 CHIP_RDY_W::new(self)
200 }
201 #[doc = "Bits 28:31"]
202 #[inline(always)]
203 #[must_use]
204 pub fn glb_id(&mut self) -> GLB_ID_W<28> {
205 GLB_ID_W::new(self)
206 }
207 #[doc = "Writes raw bits to the register."]
208 #[inline(always)]
209 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
210 self.0.bits(bits);
211 self
212 }
213}
214#[doc = "clk_cfg0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg0](index.html) module"]
215pub struct CLK_CFG0_SPEC;
216impl crate::RegisterSpec for CLK_CFG0_SPEC {
217 type Ux = u32;
218}
219#[doc = "`read()` method returns [clk_cfg0::R](R) reader structure"]
220impl crate::Readable for CLK_CFG0_SPEC {
221 type Reader = R;
222}
223#[doc = "`write(|w| ..)` method takes [clk_cfg0::W](W) writer structure"]
224impl crate::Writable for CLK_CFG0_SPEC {
225 type Writer = W;
226 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
227 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
228}
229#[doc = "`reset()` method sets clk_cfg0 to value 0"]
230impl crate::Resettable for CLK_CFG0_SPEC {
231 const RESET_VALUE: Self::Ux = 0;
232}